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@augustofg
augustofg committed Sep 5, 2024
2 parents b26def0 + 68d62d1 commit 644dfd6
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2 changes: 1 addition & 1 deletion hdl/ip_cores/CommsCtrlFPGA
Submodule CommsCtrlFPGA updated 19 files
+0 −12 .gitignore
+0 −6 rtl/Manifest.py
+0 −5 rtl/chipscope/7series/Manifest.py
+0 −3,247 rtl/chipscope/7series/ila_fofb_cc_t8_d256_s16384/ila_fofb_cc_t8_d256_s16384.xci
+0 −3,251 rtl/chipscope/7series/ila_fofb_cc_t8_d256_s4096_cap/ila_fofb_cc_t8_d256_s4096_cap.xci
+0 −3,251 rtl/chipscope/7series/ila_fofb_cc_t8_d256_s8192_cap/ila_fofb_cc_t8_d256_s8192_cap.xci
+3 −2 rtl/fofb_cc_fa_if/Manifest.py
+281 −315 rtl/fofb_cc_fa_if/coregen/artix7/fofb_cc_fa_if_bram_16_to_32/fofb_cc_fa_if_bram_16_to_32.xci
+0 −929 rtl/fofb_cc_fa_if/coregen/artix7/fofb_cc_fa_if_bram_16_to_32/fofb_cc_fa_if_bram_16_to_32_sim_netlist.vhdl
+281 −314 rtl/fofb_cc_fa_if/coregen/artix7/fofb_cc_fa_if_bram_32_to_32/fofb_cc_fa_if_bram_32_to_32.xci
+0 −945 rtl/fofb_cc_fa_if/coregen/artix7/fofb_cc_fa_if_bram_32_to_32/fofb_cc_fa_if_bram_32_to_32_sim_netlist.vhdl
+0 −4 rtl/fofb_cc_gtp7_if/rtl/vhdl/fofb_cc_gt_if.vhd
+6 −0 rtl/fofb_cc_pkg/rtl/vhdl/fofb_cc_pkg.vhd
+2 −1 rtl/fofb_cc_rx_fifo/Manifest.py
+484 −574 rtl/fofb_cc_rx_fifo/coregen/artix7/fofb_cc_rx_fifo.xci
+0 −8,125 rtl/fofb_cc_rx_fifo/coregen/artix7/fofb_cc_rx_fifo_sim_netlist.vhdl
+2 −1 rtl/fofb_cc_tx_fifo/Manifest.py
+484 −581 rtl/fofb_cc_tx_fifo/coregen/artix7/fofb_cc_tx_fifo.xci
+0 −6,658 rtl/fofb_cc_tx_fifo/coregen/artix7/fofb_cc_tx_fifo_sim_netlist.vhdl
2 changes: 1 addition & 1 deletion hdl/ip_cores/infra-cores
Submodule infra-cores updated 152 files
11 changes: 10 additions & 1 deletion hdl/modules/bpm_cores_pkg.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -232,7 +232,8 @@ package bpm_cores_pkg is
g_k_width : natural := 25;
g_offset_width : natural := 32;
g_IQ_width : natural := 32;
g_adc_gain_width : natural := 25);
g_adc_gain_width : natural := 25;
g_adc_offset_width : natural := 16);
port (
adc_ch0_i : in std_logic_vector(g_input_width-1 downto 0);
adc_ch1_i : in std_logic_vector(g_input_width-1 downto 0);
Expand All @@ -254,6 +255,14 @@ package bpm_cores_pkg is
adc_ch1_swclk_1_gain_i : in std_logic_vector(g_adc_gain_width-1 downto 0);
adc_ch2_swclk_1_gain_i : in std_logic_vector(g_adc_gain_width-1 downto 0);
adc_ch3_swclk_1_gain_i : in std_logic_vector(g_adc_gain_width-1 downto 0);
adc_ch0_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);
adc_ch1_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);
adc_ch2_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);
adc_ch3_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);
adc_ch0_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);
adc_ch1_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);
adc_ch2_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);
adc_ch3_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);
offset_x_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0');
offset_y_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0');
mix_ch0_i_o : out std_logic_vector(g_IQ_width-1 downto 0);
Expand Down
15 changes: 11 additions & 4 deletions hdl/modules/machine/pbpm_fmcpico1M/machine_pkg.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,6 +43,8 @@ use ieee.numeric_std.all;
use ieee.math_real.all;

package machine_pkg is
-- NOTE: PBMs aren't synchronized to the Timing system, so no sampling
-- frequency/phase relation should be assumed between them and EBPMs.

constant c_pos_calc_with_downconv : boolean := false;

Expand All @@ -58,24 +60,29 @@ package machine_pkg is
constant c_pos_calc_sin_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_sin.nif";
constant c_pos_calc_cos_file : string := "../../../dsp-cores/hdl/modules/position_calc/dds_cos.nif";

-- TbT rate: 500 kHz
-- NOTE: This is way off EBPMs' TbT rate (~578 KHz)
constant c_pos_calc_tbt_cic_delay : natural := 1;
constant c_pos_calc_tbt_cic_stages : natural := 1;
constant c_pos_calc_tbt_ratio : natural := 2;
constant c_pos_calc_tbt_ratio : natural := 2; -- ratio between ADC and TbT rates
constant c_pos_calc_tbt_decim_width : natural := 32;

-- FOFB rate: 47.619 kHz
constant c_pos_calc_fofb_cic_delay : natural := 1;
constant c_pos_calc_fofb_cic_stages : natural := 1;
constant c_pos_calc_fofb_ratio : natural := 10;
constant c_pos_calc_fofb_ratio : natural := 21; -- ratio between ADC and FOFB rates
constant c_pos_calc_fofb_decim_width : natural := 32;

-- FAcq rate: 5.952 kHz
constant c_pos_calc_monit1_cic_delay : natural := 1;
constant c_pos_calc_monit1_cic_stages : natural := 1;
constant c_pos_calc_monit1_ratio : natural := 100; --ratio between fofb and monit 1
constant c_pos_calc_monit1_ratio : natural := 8; -- ratio between FOFB and FAcq rates
constant c_pos_calc_monit1_cic_ratio : natural := 8;

-- Monit rate: 10.352 Hz
constant c_pos_calc_monit2_cic_delay : natural := 1;
constant c_pos_calc_monit2_cic_stages : natural := 1;
constant c_pos_calc_monit2_ratio : natural := 40; -- ratio between monit 1 and 2
constant c_pos_calc_monit2_ratio : natural := 575; -- ratio between FAcq and Monit rates
constant c_pos_calc_monit2_cic_ratio : natural := 8;

constant c_pos_calc_monit_decim_width : natural := 32;
Expand Down
164 changes: 86 additions & 78 deletions hdl/modules/position_calc/position_calc.vhd
View file
Original file line number Diff line number Diff line change
Expand Up @@ -107,7 +107,10 @@ entity position_calc is
g_IQ_width : natural := 32;

-- width of adc gains
g_adc_gain_width : natural := 25
g_adc_gain_width : natural := 25;

-- Width of ADC offsets
g_adc_offset_width : natural := 16
);

port(
Expand Down Expand Up @@ -136,6 +139,16 @@ entity position_calc is
adc_ch2_swclk_1_gain_i : in std_logic_vector(g_adc_gain_width-1 downto 0);
adc_ch3_swclk_1_gain_i : in std_logic_vector(g_adc_gain_width-1 downto 0);

adc_ch0_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);
adc_ch1_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);
adc_ch2_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);
adc_ch3_swclk_0_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);

adc_ch0_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);
adc_ch1_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);
adc_ch2_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);
adc_ch3_swclk_1_offset_i : in std_logic_vector(g_adc_offset_width-1 downto 0);

offset_x_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0');
offset_y_i : in std_logic_vector(g_offset_width-1 downto 0) := (others => '0');

Expand Down Expand Up @@ -368,25 +381,30 @@ architecture rtl of position_calc is
--Signals--
-----------
type t_input is array(3 downto 0) of std_logic_vector(g_input_width-1 downto 0);
signal adc_input : t_input := (others => (others => '0'));
signal adc_input_d0 : t_input := (others => (others => '0'));
signal adc_input_d1 : t_input := (others => (others => '0'));
signal adc_input_scaled : t_input := (others => (others => '0'));
signal adc_input_offs : t_input := (others => (others => '0'));
signal adc_input_offs_scaled : t_input := (others => (others => '0'));

type t_input_gain is array(3 downto 0) of std_logic_vector(g_adc_gain_width-1 downto 0);
signal adc_input_gain : t_input_gain := (others => (others => '0'));
signal adc_input_swclk_0_gain : t_input_gain := (others => (others => '0'));
signal adc_input_swclk_1_gain : t_input_gain := (others => (others => '0'));
type t_adc_gain_arr is array(3 downto 0) of std_logic_vector(g_adc_gain_width-1 downto 0);
signal adc_gain_arr : t_adc_gain_arr := (others => (others => '0'));
signal adc_gain_swclk_0_arr : t_adc_gain_arr := (others => (others => '0'));
signal adc_gain_swclk_1_arr : t_adc_gain_arr := (others => (others => '0'));

type t_adc_offset_arr is array(3 downto 0) of std_logic_vector(g_adc_offset_width-1 downto 0);
signal adc_offset_arr : t_adc_offset_arr := (others => (others => '0'));
signal adc_offset_swclk_0_arr : t_adc_offset_arr := (others => (others => '0'));
signal adc_offset_swclk_1_arr : t_adc_offset_arr := (others => (others => '0'));

type t_input_valid is array(3 downto 0) of std_logic;
signal adc_input_valid : t_input_valid := (others => '0');
signal iq_valid : t_input_valid := (others => '0');
signal adc_input_scaled_valid : t_input_valid := (others => '0');
signal adc_input_offs_valid : t_input_valid := (others => '0');
signal adc_input_offs_scaled_valid : t_input_valid := (others => '0');
signal adc_input_valid_d1 : std_logic := '0';

type t_input_tag is array(3 downto 0) of std_logic_vector(c_adc_tag_width-1 downto 0);
signal adc_input_tag : t_input_tag := (others => (others => '0'));
signal adc_input_scaled_tag : t_input_tag := (others => (others => '0'));
signal adc_input_offs_tag : t_input_tag := (others => (others => '0'));
signal adc_input_offs_scaled_tag : t_input_tag := (others => (others => '0'));
signal adc_input_tag_d1 : std_logic_vector(c_adc_tag_width-1 downto 0) := (others => '0');

signal full_i_tag : t_input_tag := (others => (others => '0'));
Expand Down Expand Up @@ -458,50 +476,55 @@ begin
adc_input_d0(2) <= adc_ch2_i;
adc_input_d0(3) <= adc_ch3_i;

adc_input_swclk_0_gain(0) <= adc_ch0_swclk_0_gain_i;
adc_input_swclk_0_gain(1) <= adc_ch1_swclk_0_gain_i;
adc_input_swclk_0_gain(2) <= adc_ch2_swclk_0_gain_i;
adc_input_swclk_0_gain(3) <= adc_ch3_swclk_0_gain_i;
adc_gain_swclk_0_arr(0) <= adc_ch0_swclk_0_gain_i;
adc_gain_swclk_0_arr(1) <= adc_ch1_swclk_0_gain_i;
adc_gain_swclk_0_arr(2) <= adc_ch2_swclk_0_gain_i;
adc_gain_swclk_0_arr(3) <= adc_ch3_swclk_0_gain_i;

adc_gain_swclk_1_arr(0) <= adc_ch0_swclk_1_gain_i;
adc_gain_swclk_1_arr(1) <= adc_ch1_swclk_1_gain_i;
adc_gain_swclk_1_arr(2) <= adc_ch2_swclk_1_gain_i;
adc_gain_swclk_1_arr(3) <= adc_ch3_swclk_1_gain_i;

adc_input_swclk_1_gain(0) <= adc_ch0_swclk_1_gain_i;
adc_input_swclk_1_gain(1) <= adc_ch1_swclk_1_gain_i;
adc_input_swclk_1_gain(2) <= adc_ch2_swclk_1_gain_i;
adc_input_swclk_1_gain(3) <= adc_ch3_swclk_1_gain_i;
adc_offset_swclk_0_arr(0) <= adc_ch0_swclk_0_offset_i;
adc_offset_swclk_0_arr(1) <= adc_ch1_swclk_0_offset_i;
adc_offset_swclk_0_arr(2) <= adc_ch2_swclk_0_offset_i;
adc_offset_swclk_0_arr(3) <= adc_ch3_swclk_0_offset_i;

-- adc gains mux (delay: 1 clock cycle)
-- each adc channel has two associated gains, one for each rffe switch state (adc_tag_i)
p_adc_gains_mux: process(clk_i)
adc_offset_swclk_1_arr(0) <= adc_ch0_swclk_1_offset_i;
adc_offset_swclk_1_arr(1) <= adc_ch1_swclk_1_offset_i;
adc_offset_swclk_1_arr(2) <= adc_ch2_swclk_1_offset_i;
adc_offset_swclk_1_arr(3) <= adc_ch3_swclk_1_offset_i;

-- ADCs' offset (and gain mux) stage
p_adc_offs_stage : process(clk_i)
begin
if rising_edge(clk_i) then
-- 1st pipeline stage: mux offset
if adc_tag_i(0) = '0' then
adc_input_gain <= adc_input_swclk_0_gain;
else -- adc_tag_i(0) = '1'
adc_input_gain <= adc_input_swclk_1_gain;
adc_offset_arr <= adc_offset_swclk_0_arr;
else
adc_offset_arr <= adc_offset_swclk_1_arr;
end if;
adc_input_d1 <= adc_input_d0;
adc_input_tag_d1 <= adc_tag_i;
adc_input_valid_d1 <= adc_valid_i;

-- 2nd pipeline stage: apply the offset, mux gain
for chan in 3 downto 0 loop
adc_input_offs(chan) <= std_logic_vector(
signed(adc_input_d1(chan)) - signed(adc_offset_arr(chan)));
end loop;
adc_input_offs_tag <= (others => adc_input_tag_d1);
adc_input_offs_valid <= (others => adc_input_valid_d1);

if adc_input_tag_d1(0) = '0' then
adc_gain_arr <= adc_gain_swclk_0_arr;
else
adc_gain_arr <= adc_gain_swclk_1_arr;
end if;
end if;
end process;

-- pipeline stage to level the delay of p_adc_gains_mux
cmp_pipeline_adc_input_valid : pipeline
generic map (
g_width => 1,
g_depth => 1)
port map (
data_i(0) => adc_valid_i,
clk_i => clk_i,
ce_i => '1',
data_o(0) => adc_input_valid_d1);

-- pipeline stage to level the delay of p_adc_gains_mux
cmp_pipeline_adc_input_tag : pipeline
generic map (
g_width => 1,
g_depth => 1)
port map (
data_i => adc_tag_i,
clk_i => clk_i,
ce_i => '1',
data_o => adc_input_tag_d1);
end process p_adc_offs_stage;

-- Reset fof TBT rates sync'ed with external signal
gen_ddc : for chan in 3 downto 0 generate
Expand Down Expand Up @@ -562,21 +585,6 @@ begin
ratio_i => c_monit2_cic_ratio_slv,
strobe_o => ce_monit2(chan));

-- pipeline stage to level the delay of p_adc_gains_mux
cmp_pipeline_adc_input : pipeline
generic map (
g_width => g_input_width,
g_depth => 1)
port map (
data_i => adc_input_d0(chan),
clk_i => clk_i,
ce_i => '1',
data_o => adc_input_d1(chan));

adc_input(chan) <= adc_input_d1(chan);
adc_input_tag(chan) <= adc_input_tag_d1;
adc_input_valid(chan) <= adc_input_valid_d1;

cmp_generic_multiplier : generic_multiplier
generic map (
g_a_width => g_input_width,
Expand All @@ -587,13 +595,13 @@ begin
g_round_convergent => 1,
g_levels => 1)
port map (
a_i => adc_input(chan),
b_i => adc_input_gain(chan),
valid_i => adc_input_valid(chan),
tag_i => adc_input_tag(chan),
p_o => adc_input_scaled(chan),
valid_o => adc_input_scaled_valid(chan),
tag_o => adc_input_scaled_tag(chan),
a_i => adc_input_offs(chan),
b_i => adc_gain_arr(chan),
valid_i => adc_input_offs_valid(chan),
tag_i => adc_input_offs_tag(chan),
p_o => adc_input_offs_scaled(chan),
valid_o => adc_input_offs_scaled_valid(chan),
tag_o => adc_input_offs_scaled_tag(chan),
ce_i => '1',
clk_i => clk_i,
rst_i => rst_i);
Expand All @@ -614,9 +622,9 @@ begin
rst_i => rst_i,
clk_i => clk_i,
ce_i => ce_adc(chan),
signal_i => adc_input_scaled(chan),
valid_i => adc_input_scaled_valid(chan),
tag_i => adc_input_scaled_tag(chan),
signal_i => adc_input_offs_scaled(chan),
valid_i => adc_input_offs_scaled_valid(chan),
tag_i => adc_input_offs_scaled_tag(chan),
i_o => full_i(chan),
q_o => full_q(chan),
valid_o => iq_valid(chan),
Expand Down Expand Up @@ -761,8 +769,8 @@ begin
-- rate, so we don't have to
-- change them downstream
ce_out_i => ce_tbt_cordic(chan),
valid_i => adc_input_scaled_valid(chan),
data_i => adc_input_scaled(chan),
valid_i => adc_input_offs_scaled_valid(chan),
data_i => adc_input_offs_scaled(chan),
ratio_i => c_tbt_ratio_slv,
data_tag_i => tbt_tag_i,
data_tag_en_i => tbt_tag_en_i,
Expand Down Expand Up @@ -797,9 +805,9 @@ begin
rst_i => rst_i,
ce_i => ce_adc(chan),
ce_out_i => ce_fofb_cordic(chan),
valid_i => adc_input_scaled_valid(chan),
data_i => adc_input_scaled(chan),
data_tag_i => adc_input_scaled_tag(chan),
valid_i => adc_input_offs_scaled_valid(chan),
data_i => adc_input_offs_scaled(chan),
data_tag_i => adc_input_offs_scaled_tag(chan),
-- Don't use CIC synchronization feature
data_tag_en_i => '0',
data_mask_num_samples_beg_i => (others => '0'),
Expand Down
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