Skip to content

Commit

Permalink
Merge remote-tracking branch 'irixxxx/master' into master
Browse files Browse the repository at this point in the history
irixxxx committed Jun 15, 2024
2 parents ad93670 + 7647f87 commit dab9c6e
Showing 54 changed files with 832 additions and 689 deletions.
40 changes: 25 additions & 15 deletions Makefile
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
$(LD) ?= $(CC)
TARGET ?= PicoDrive
TARGET ?= picodrive
ASAN ?= 0
DEBUG ?= 0
CFLAGS += -I$(PWD)
@@ -102,7 +102,7 @@ asm_32xmemory ?= 1
else
use_fame ?= 1
use_cz80 ?= 1
ifneq (,$(filter x86% i386% mips% aarch% riscv% powerpc% ppc%, $(ARCH)))
ifneq (,$(filter x86% i386% i686% mips% aarch% riscv% powerpc% ppc%, $(ARCH)))
use_sh2drc ?= 1
endif
endif
@@ -111,15 +111,15 @@ endif

# TODO this should somehow go to the platform directory?
ifeq "$(PLATFORM)" "generic"
$(TARGET).zip: $(TARGET)
PicoDrive.zip: $(TARGET)
$(RM) -rf .od_data
mkdir .od_data
cp -r platform/linux/skin .od_data
cp platform/game_def.cfg .od_data
cp $< .od_data/PicoDrive
$(STRIP) .od_data/PicoDrive
cd .od_data && zip -9 -r ../$@ *
all: $(TARGET).zip
all: PicoDrive.zip
endif

ifeq "$(PLATFORM)" "opendingux"
@@ -134,22 +134,22 @@ ifeq "$(PLATFORM)" "opendingux"

ifneq (,$(filter %__DINGUX__, $(CFLAGS)))
# "legacy" dingux without opk support
$(TARGET)-dge.zip: .od_data
PicoDrive-dge.zip: .od_data
rm -f .od_data/default.*.desktop
cd .od_data && zip -9 -r ../$@ *
all: $(TARGET)-dge.zip
all: PicoDrive-dge.zip
CFLAGS += -DSDL_SURFACE_SW # some legacy dinguces had bugs in HWSURFACE
else
ifneq (,$(filter %__MIYOO__, $(CFLAGS)))
$(TARGET)-miyoo.zip: .od_data
PicoDrive-miyoo.zip: .od_data
rm -f .od_data/default.*.desktop .od_data/PicoDrive.dge
cd .od_data && zip -9 -r ../$@ *
all: $(TARGET)-miyoo.zip
all: PicoDrive-miyoo.zip
else
$(TARGET).opk: .od_data
PicoDrive.opk: .od_data
rm -f .od_data/PicoDrive.dge
mksquashfs .od_data $@ -all-root -noappend -no-exports -no-xattrs
all: $(TARGET).opk
all: PicoDrive.opk
endif
endif

@@ -328,14 +328,24 @@ CHDR_OBJS += $(CHDR)/src/libchdr_chd.o $(CHDR)/src/libchdr_cdrom.o
CHDR_OBJS += $(CHDR)/src/libchdr_flac.o
CHDR_OBJS += $(CHDR)/src/libchdr_bitstream.o $(CHDR)/src/libchdr_huffman.o

# lzma - use 19.00 as newer versions have compile problems with libretro platforms
LZMA = $(CHDR)/deps/lzma-19.00
LZMA = $(CHDR)/deps/lzma-24.05
LZMA_OBJS += $(LZMA)/src/CpuArch.o $(LZMA)/src/Alloc.o $(LZMA)/src/LzmaEnc.o
LZMA_OBJS += $(LZMA)/src/Sort.o $(LZMA)/src/LzmaDec.o $(LZMA)/src/LzFind.o
LZMA_OBJS += $(LZMA)/src/Delta.o
$(LZMA_OBJS): CFLAGS += -D_7ZIP_ST

OBJS += $(CHDR_OBJS)
$(LZMA_OBJS): CFLAGS += -DZ7_ST -Wno-unused

ZSTD = $(CHDR)/deps/zstd-1.5.6/lib
ZSTD_OBJS += $(ZSTD)/common/entropy_common.o $(ZSTD)/common/error_private.o
ZSTD_OBJS += $(ZSTD)/common/fse_decompress.o $(ZSTD)/common/xxhash.o
ZSTD_OBJS += $(ZSTD)/common/zstd_common.o
ZSTD_OBJS += $(ZSTD)/decompress/huf_decompress.o
ZSTD_OBJS += $(ZSTD)/decompress/huf_decompress_amd64.o
ZSTD_OBJS += $(ZSTD)/decompress/zstd_ddict.o
ZSTD_OBJS += $(ZSTD)/decompress/zstd_decompress_block.o
ZSTD_OBJS += $(ZSTD)/decompress/zstd_decompress.o
$(ZSTD_OBJS) $(CHDR_OBJS): CFLAGS += -I$(ZSTD) -Wno-unused

OBJS += $(CHDR_OBJS) $(ZSTD_OBJS)
ifneq ($(STATIC_LINKING), 1)
OBJS += $(LZMA_OBJS)
endif
61 changes: 30 additions & 31 deletions cpu/drc/emit_arm.c
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
/*
* Basic macros to emit ARM instructions and some utils
* Copyright (C) 2008,2009,2010 notaz
* Copyright (C) 2019 kub
* Copyright (C) 2019-2024 kub
*
* This work is licensed under the terms of MAME license.
* See COPYING file in the top-level directory.
@@ -425,11 +425,11 @@ static void emith_flush(void)
#define EOP_MSR_IMM(ror2,imm) EOP_C_MSR_IMM(A_COND_AL,ror2,imm)
#define EOP_MSR_REG(rm) EOP_C_MSR_REG(A_COND_AL,rm)

#define EOP_MOVW(rd,imm) \
EMIT(0xe3000000 | ((rd)<<12) | ((imm)&0xfff) | (((imm)<<4)&0xf0000), M1(rd), NO)
#define EOP_MOVW(cond,rd,imm) \
EMIT(((cond)<<28) | 0x03000000 | ((rd)<<12) | ((imm)&0xfff) | (((imm)<<4)&0xf0000), M1(rd), NO)

#define EOP_MOVT(rd,imm) \
EMIT(0xe3400000 | ((rd)<<12) | (((imm)>>16)&0xfff) | (((imm)>>12)&0xf0000), M1(rd), NO)
#define EOP_MOVT(cond,rd,imm) \
EMIT(((cond)<<28) | 0x03400000 | ((rd)<<12) | (((imm)>>16)&0xfff) | (((imm)>>12)&0xf0000), M1(rd), NO)

// host literal pool; must be significantly smaller than 1024 (max LDR offset = 4096)
#define MAX_HOST_LITERALS 128
@@ -486,9 +486,9 @@ static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int
if (op == A_OP_MVN)
imm = ~imm;
// ...prefer movw/movt
EOP_MOVW(rd, imm);
EOP_MOVW(cond,rd, imm);
if (imm & 0xffff0000)
EOP_MOVT(rd, imm);
EOP_MOVT(cond,rd, imm);
return;
}
#else
@@ -512,7 +512,7 @@ static void emith_op_imm2(int cond, int s, int op, int rd, int rn, unsigned int
EOP_C_DOP_IMM(cond, A_OP_ADD, 0,rd,rd,0,o);
else if (o < 0)
EOP_C_DOP_IMM(cond, A_OP_SUB, 0,rd,rd,0,-o);
return;
return;
}
#endif
break;
@@ -1196,7 +1196,7 @@ static inline void emith_pool_adjust(int tcache_offs, int move_offs)

#define emith_jump_at(ptr, target) do { \
u32 *ptr_ = (u32 *)ptr; \
u32 val_ = (u32 *)(target) - (u32 *)(ptr) - 2; \
u32 val_ = (u32 *)(target) - ptr_ - 2; \
EOP_C_B_PTR(ptr_, A_COND_AL, 0, val_ & 0xffffff); \
} while (0)
#define emith_jump_at_size() 4
@@ -1329,10 +1329,11 @@ static inline void emith_pool_adjust(int tcache_offs, int move_offs)
int t2 = rcache_get_tmp(); \
int t3 = rcache_get_tmp(); \
/* if (sr < 0) return */ \
emith_asrf(t2, sr, 12); \
emith_cmp_r_imm(sr, 0); \
EMITH_JMP_START(DCOND_LE); \
/* turns = sr.cycles / cycles */ \
emith_move_r_imm(t3, (u32)((1ULL<<32) / (cycles)) + 1); \
emith_asr(t2, sr, 12); \
emith_move_r_imm(t3, (u32)((1ULL<<32) / (cycles))); \
emith_mul_u64(t1, t2, t2, t3); /* multiply by 1/x */ \
rcache_free_tmp(t3); \
if (reg >= 0) { \
@@ -1362,13 +1363,11 @@ static inline void emith_pool_adjust(int tcache_offs, int move_offs)
} while (0)

#define emith_carry_to_t(srr, is_sub) do { \
if (is_sub) { /* has inverted C on ARM */ \
emith_bic_r_imm(srr, 1); \
if (is_sub) /* has inverted C on ARM */ \
emith_or_r_imm_c(A_COND_CC, srr, 1); \
emith_bic_r_imm_c(A_COND_CS, srr, 1); \
} else { \
else \
emith_or_r_imm_c(A_COND_CS, srr, 1); \
emith_bic_r_imm_c(A_COND_CC, srr, 1); \
} \
} while (0)

#define emith_t_to_carry(srr, is_sub) do { \
@@ -1428,16 +1427,16 @@ static inline void emith_pool_adjust(int tcache_offs, int move_offs)
emith_sext(mh, mh, 16); \
emith_mula_s64(ml, mh, rn, rm); \
/* overflow if top 17 bits of MACH aren't all 1 or 0 */ \
/* to check: add MACH[15] to MACH[31:16]. this is 0 if no overflow */ \
emith_asrf(rn, mh, 16); /* sum = (MACH>>16) + ((MACH>>15)&1) */ \
emith_adcf_r_imm(rn, 0); /* (MACH>>15) is in carry after shift */ \
EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> ov */ \
emith_move_r_imm_c(DCOND_NE, ml, 0x0000); /* -overflow */ \
emith_move_r_imm_c(DCOND_NE, mh, 0x8000); \
EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> +ovl */ \
emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0xffffffff */ \
emith_sub_r_imm_c(DCOND_GT, mh, 1); /* 0x00007fff */ \
EMITH_SJMP_END(DCOND_LE); \
/* to check: add MACH >> 31 to MACH >> 15. this is 0 if no overflow */ \
emith_asr(rn, mh, 15); \
emith_addf_r_r_r_lsr(rn, rn, mh, 31); \
EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> -ovl */ \
emith_move_r_imm_c(DCOND_NE, ml, 0x00000000); \
emith_move_r_imm_c(DCOND_NE, mh, 0x00008000); \
EMITH_SJMP_START(DCOND_MI); /* sum > 0 -> +ovl */ \
emith_sub_r_imm_c(DCOND_PL, ml, 1); /* 0xffffffff */ \
emith_sub_r_imm_c(DCOND_PL, mh, 1); /* 0x00007fff */ \
EMITH_SJMP_END(DCOND_MI); \
EMITH_SJMP_END(DCOND_EQ); \
EMITH_SJMP2_END(DCOND_NE); \
} while (0)
@@ -1457,10 +1456,10 @@ static inline void emith_pool_adjust(int tcache_offs, int move_offs)
EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> overflow */ \
/* XXX: LSB signalling only in SH1, or in SH2 too? */ \
emith_move_r_imm_c(DCOND_NE, mh, 0x00000001); /* LSB of MACH */ \
emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* negative ovrfl */ \
EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> positive ovrfl */ \
emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0x7fffffff */ \
EMITH_SJMP_END(DCOND_LE); \
emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* -ovrfl */ \
EMITH_SJMP_START(DCOND_MI); /* sum > 0 -> +ovrfl */ \
emith_sub_r_imm_c(DCOND_PL, ml, 1); /* 0x7fffffff */ \
EMITH_SJMP_END(DCOND_MI); \
EMITH_SJMP_END(DCOND_EQ); \
EMITH_SJMP2_END(DCOND_NE); \
} while (0)
@@ -1494,7 +1493,7 @@ static void emith_sync_t(int sr)
else if (tcond == A_COND_NV)
emith_bic_r_imm(sr, T);
else if (tcond >= 0) {
emith_bic_r_imm_c(emith_invert_cond(tcond),sr, T);
emith_bic_r_imm(sr, T);
emith_or_r_imm_c(tcond, sr, T);
}
tcond = -1;
26 changes: 13 additions & 13 deletions cpu/drc/emit_arm64.c
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/*
* Basic macros to emit ARM A64 instructions and some utils
* Copyright (C) 2019 kub
* Copyright (C) 2019-2024 kub
*
* This work is licensed under the terms of MAME license.
* See COPYING file in the top-level directory.
@@ -1242,7 +1242,7 @@ static void emith_ldst_offs(int sz, int rd, int rn, int o9, int ld, int mode)
EMITH_JMP_START(DCOND_LE); \
/* turns = sr.cycles / cycles */ \
emith_asr(t2, sr, 12); \
emith_move_r_imm(t3, (u32)((1ULL<<32) / (cycles)) + 1); \
emith_move_r_imm(t3, (u32)((1ULL<<32) / (cycles))); \
emith_mul_u64(t1, t2, t2, t3); /* multiply by 1/x */ \
rcache_free_tmp(t3); \
if (reg >= 0) { \
@@ -1309,13 +1309,13 @@ static void emith_ldst_offs(int sz, int rd, int rn, int o9, int ld, int mode)
/* to check: add MACH >> 31 to MACH >> 15. this is 0 if no overflow */ \
emith_asr(rn, mh, 15); \
emith_addf_r_r_r_lsr(rn, rn, mh, 31); \
EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> ov */ \
emith_move_r_imm_c(DCOND_NE, ml, 0x0000); /* -overflow */ \
emith_move_r_imm_c(DCOND_NE, mh, 0x8000); \
EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> +ovl */ \
emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0xffffffff */ \
emith_sub_r_imm_c(DCOND_GT, mh, 1); /* 0x00007fff */ \
EMITH_SJMP_END(DCOND_LE); \
EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> -ovl */ \
emith_move_r_imm_c(DCOND_NE, ml, 0x00000000); \
emith_move_r_imm_c(DCOND_NE, mh, 0x00008000); \
EMITH_SJMP_START(DCOND_MI); /* sum > 0 -> +ovl */ \
emith_sub_r_imm_c(DCOND_PL, ml, 1); /* 0xffffffff */ \
emith_sub_r_imm_c(DCOND_PL, mh, 1); /* 0x00007fff */ \
EMITH_SJMP_END(DCOND_MI); \
EMITH_SJMP_END(DCOND_EQ); \
EMITH_SJMP_END(DCOND_EQ); \
} while (0)
@@ -1336,10 +1336,10 @@ static void emith_ldst_offs(int sz, int rd, int rn, int o9, int ld, int mode)
EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> overflow */ \
/* XXX: LSB signalling only in SH1, or in SH2 too? */ \
emith_move_r_imm_c(DCOND_NE, mh, 0x00000001); /* LSB of MACH */ \
emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* negative ovrfl */ \
EMITH_SJMP_START(DCOND_LE); /* sum > 0 -> positive ovrfl */ \
emith_sub_r_imm_c(DCOND_GT, ml, 1); /* 0x7fffffff */ \
EMITH_SJMP_END(DCOND_LE); \
emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* -ovrfl */ \
EMITH_SJMP_START(DCOND_MI); /* sum > 0 -> +ovrfl */ \
emith_sub_r_imm_c(DCOND_PL, ml, 1); /* 0x7fffffff */ \
EMITH_SJMP_END(DCOND_MI); \
EMITH_SJMP_END(DCOND_EQ); \
EMITH_SJMP_END(DCOND_EQ); \
} while (0)
34 changes: 21 additions & 13 deletions cpu/drc/emit_mips.c
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
/*
* Basic macros to emit MIPS32/MIPS64 Release 1 or 2 instructions and some utils
* Copyright (C) 2019 kub
* Copyright (C) 2019-2024 kub
*
* This work is licensed under the terms of MAME license.
* See COPYING file in the top-level directory.
@@ -1671,12 +1671,20 @@ static NOINLINE void host_instructions_updated(void *base, void *end, int force)
asm volatile(
" rdhwr %2, $1;"
" bal 0f;" // needed to allow for jr.hb:
#if _MIPS_SZPTR == 64
"0: daddiu $ra, $ra, 3f-0b;" // set ra to insn after jr.hb
#else
"0: addiu $ra, $ra, 3f-0b;" // set ra to insn after jr.hb
#endif
" beqz %2, 3f;"

"1: synci 0(%0);"
" sltu %3, %0, %1;"
#if _MIPS_SZPTR == 64
" daddu %0, %0, %2;"
#else
" addu %0, %0, %2;"
#endif
" bnez %3, 1b;"

" sync;"
@@ -1736,7 +1744,7 @@ static NOINLINE void host_instructions_updated(void *base, void *end, int force)
EMITH_JMP_START(DCOND_LE); \
/* turns = sr.cycles / cycles */ \
emith_asr(t2, sr, 12); \
emith_move_r_imm(t3, (u32)((1ULL<<32) / (cycles)) + 1); \
emith_move_r_imm(t3, (u32)((1ULL<<32) / (cycles))); \
emith_mul_u64(t1, t2, t2, t3); /* multiply by 1/x */ \
rcache_free_tmp(t3); \
if (reg >= 0) { \
@@ -1806,13 +1814,13 @@ static NOINLINE void host_instructions_updated(void *base, void *end, int force)
emith_asr(rn, mh, 15); \
emith_add_r_r_r_lsr(rn, rn, mh, 31); /* sum = (MACH>>31)+(MACH>>15) */ \
emith_teq_r_r(rn, Z0); /* (need only N and Z flags) */ \
EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> ov */ \
emith_move_r_imm_c(DCOND_NE, ml, 0x0000); /* -overflow */ \
emith_move_r_imm_c(DCOND_NE, mh, 0x8000); \
EMITH_SJMP_START(DCOND_PL); /* sum > 0 -> +ovl */ \
emith_sub_r_imm_c(DCOND_MI, ml, 1); /* 0xffffffff */ \
emith_sub_r_imm_c(DCOND_MI, mh, 1); /* 0x00007fff */ \
EMITH_SJMP_END(DCOND_PL); \
EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> -ovl */ \
emith_move_r_imm_c(DCOND_NE, ml, 0x00000000); \
emith_move_r_imm_c(DCOND_NE, mh, 0x00008000); \
EMITH_SJMP_START(DCOND_MI); /* sum > 0 -> +ovl */ \
emith_sub_r_imm_c(DCOND_PL, ml, 1); /* 0xffffffff */ \
emith_sub_r_imm_c(DCOND_PL, mh, 1); /* 0x00007fff */ \
EMITH_SJMP_END(DCOND_MI); \
EMITH_SJMP_END(DCOND_EQ); \
EMITH_SJMP_END(DCOND_EQ); \
} while (0)
@@ -1835,10 +1843,10 @@ static NOINLINE void host_instructions_updated(void *base, void *end, int force)
EMITH_SJMP_START(DCOND_EQ); /* sum != 0 -> overflow */ \
/* XXX: LSB signalling only in SH1, or in SH2 too? */ \
emith_move_r_imm_c(DCOND_NE, mh, 0x00000001); /* LSB of MACH */ \
emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* negative ovrfl */ \
EMITH_SJMP_START(DCOND_PL); /* sum > 0 -> positive ovrfl */ \
emith_sub_r_imm_c(DCOND_MI, ml, 1); /* 0x7fffffff */ \
EMITH_SJMP_END(DCOND_PL); \
emith_move_r_imm_c(DCOND_NE, ml, 0x80000000); /* -ovrfl */ \
EMITH_SJMP_START(DCOND_MI); /* sum < 0 -> +ovrfl */ \
emith_sub_r_imm_c(DCOND_PL, ml, 1); /* 0x7fffffff */ \
EMITH_SJMP_END(DCOND_MI); \
EMITH_SJMP_END(DCOND_EQ); \
EMITH_SJMP_END(DCOND_EQ); \
} while (0)
Loading

7 comments on commit dab9c6e

@LibretroAdmin
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Hi @irixxxx , there is a build failure now for libnx -
https://git.libretro.com/libretro/picodrive/-/jobs/5332719

@irixxxx
Copy link
Collaborator Author

@irixxxx irixxxx commented on dab9c6e Jun 15, 2024 via email

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@rtissera
Copy link

@rtissera rtissera commented on dab9c6e Jun 15, 2024 via email

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@irixxxx
Copy link
Collaborator Author

@irixxxx irixxxx commented on dab9c6e Jun 15, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@LibretroAdmin you need to kick the pipeline. It's somehow not registering my last commit.

@rtissera
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Unrelated @LibretroAdmin @irixxxx but please have a look at rtissera/libchdr#126

@irixxxx
Copy link
Collaborator Author

@irixxxx irixxxx commented on dab9c6e Jun 15, 2024

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Hi @LibretroAdmin, the gitlab miror got somehow in disarray:

This project is mirrored from https://*****@github.com/libretro/picodrive.git. Pull mirroring failed 30 minutes ago.
Last successful update 1 hour ago. This branch has diverged from upstream. 

I can maybe fix this by rolling back the master to the commit hash on gitlab and add commits again, else you'd probably need to force-pull the thing. Yes, that fixes it, at the price of some merge comment clutter in the repo.

@irixxxx
Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

OK, it compiles successfully now.
You should consider having the buildbot compile on pushes to branches. That would allow me to test changes like this in advance. As it is now, I can only push to master to check whether all builds still work.

Please sign in to comment.