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Remove "U" flag from open() statements in CPU Opcode Generators #98

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Remove "U" flag from open() statements in CPU Opcode Generators #98

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114 changes: 54 additions & 60 deletions src/emu/cpu/arcompact/arcompact_make.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -351,85 +351,79 @@ def EmitGroup17(f,funcname, opname, opexecute):


try:
f = open(sys.argv[1], "w")
except Exception:
err = sys.exc_info()[1]
sys.stderr.write("cannot write file %s [%s]\n" % (sys.argv[1], err))
sys.exit(1)


EmitGroup04(f, "04_00", "ADD", "UINT32 result = b + c;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_Handle_NZCV_ADD_Flags )

EmitGroup04(f, "04_02", "SUB", "UINT32 result = b - c;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )

EmitGroup04(f, "04_04", "AND", "UINT32 result = b & c;", "if (areg != LIMM_REG) { m_regs[areg] = result; }", "if (breg != LIMM_REG) { m_regs[breg] = result; }", 0,0, -1, EmitGroup04_Handle_NZ_Flags )
EmitGroup04(f, "04_05", "OR", "UINT32 result = b | c;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_06", "BIC", "UINT32 result = b & (~c);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_07", "XOR", "UINT32 result = b ^ c;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
with open(sys.argv[1], "w") as f:
EmitGroup04(f, "04_00", "ADD", "UINT32 result = b + c;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_Handle_NZCV_ADD_Flags )

EmitGroup04(f, "04_0a", "MOV", "UINT32 result = c;", "m_regs[breg] = result;", "m_regs[breg] = result;", 1,1, -1, EmitGroup04_Handle_NZ_Flags ) # special case, result always goes to breg
EmitGroup04(f, "04_02", "SUB", "UINT32 result = b - c;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )

EmitGroup04(f, "04_0e", "RSUB", "UINT32 result = c - b;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_0f", "BSET", "UINT32 result = b | (1 << (c & 0x1f));", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_04", "AND", "UINT32 result = b & c;", "if (areg != LIMM_REG) { m_regs[areg] = result; }", "if (breg != LIMM_REG) { m_regs[breg] = result; }", 0,0, -1, EmitGroup04_Handle_NZ_Flags )
EmitGroup04(f, "04_05", "OR", "UINT32 result = b | c;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_06", "BIC", "UINT32 result = b & (~c);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_07", "XOR", "UINT32 result = b ^ c;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )

EmitGroup04(f, "04_13", "BMSK", "UINT32 result = b & ((1<<(c+1))-1);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_0a", "MOV", "UINT32 result = c;", "m_regs[breg] = result;", "m_regs[breg] = result;", 1,1, -1, EmitGroup04_Handle_NZ_Flags ) # special case, result always goes to breg

EmitGroup04(f, "04_0e", "RSUB", "UINT32 result = c - b;", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_0f", "BSET", "UINT32 result = b | (1 << (c & 0x1f));", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )

EmitGroup04(f, "04_14", "ADD1", "UINT32 result = b + (c << 1);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_15", "ADD2", "UINT32 result = b + (c << 2);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_16", "ADD3", "UINT32 result = b + (c << 3);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_17", "SUB1", "UINT32 result = b - (c << 1);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_18", "SUB2", "UINT32 result = b - (c << 2);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_19", "SUB3", "UINT32 result = b - (c << 3);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_13", "BMSK", "UINT32 result = b & ((1<<(c+1))-1);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )

EmitGroup04(f, "04_2a", "LR", "m_regs[breg] = READAUX(c);", "", "", 1,1, -1, EmitGroup04_no_Flags ) # this can't be conditional (todo)
EmitGroup04(f, "04_2b", "SR", "WRITEAUX(c,b);", "", "", 1,0, -1, EmitGroup04_no_Flags ) # this can't be conditional (todo)

EmitGroup04(f, "04_14", "ADD1", "UINT32 result = b + (c << 1);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_15", "ADD2", "UINT32 result = b + (c << 2);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_16", "ADD3", "UINT32 result = b + (c << 3);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_17", "SUB1", "UINT32 result = b - (c << 1);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_18", "SUB2", "UINT32 result = b - (c << 2);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "04_19", "SUB3", "UINT32 result = b - (c << 3);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )

EmitGroup04(f, "04_2a", "LR", "m_regs[breg] = READAUX(c);", "", "", 1,1, -1, EmitGroup04_no_Flags ) # this can't be conditional (todo)
EmitGroup04(f, "04_2b", "SR", "WRITEAUX(c,b);", "", "", 1,0, -1, EmitGroup04_no_Flags ) # this can't be conditional (todo)

EmitGroup04(f, "05_00", "ASL", "UINT32 result = b << (c&0x1f);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "05_01", "LSR", "UINT32 result = b >> (c&0x1f);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )

# the 04_2f subgroup uses the same encoding, but the areg is already used as sub-opcode select, so any modes relying on areg bits for other reasons (sign, condition) (modes 10, 11m0, 11m1) are illegal. the destination is also breg not areg
EmitGroup04(f, "04_2f_02", "LSR1", "UINT32 result = c >> 1;", "m_regs[breg] = result;","", 2,1, -1, EmitGroup04_Handle_NZC_LSR1_Flags ) # no alt handler (invalid path)
EmitGroup04(f, "04_2f_03", "ROR", "int shift = 1; UINT32 mask = (1 << (shift)) - 1; mask <<= (32-shift); UINT32 result = ((c >> shift) & ~mask) | ((c << (32-shift)) & mask);", "m_regs[breg] = result;","", 2,1, -1, EmitGroup04_Handle_NZC_LSR1_Flags )

EmitGroup04(f, "05_00", "ASL", "UINT32 result = b << (c&0x1f);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )
EmitGroup04(f, "05_01", "LSR", "UINT32 result = b >> (c&0x1f);", "m_regs[areg] = result;", "m_regs[breg] = result;", 0,0, -1, EmitGroup04_unsupported_Flags )

EmitGroup04(f, "04_2f_07", "EXTB", "UINT32 result = c & 0x000000ff;", "m_regs[breg] = result;","", 2,1, -1, EmitGroup04_unsupported_Flags ) # ^
EmitGroup04(f, "04_2f_08", "EXTW", "UINT32 result = c & 0x0000ffff;", "m_regs[breg] = result;","", 2,1, -1, EmitGroup04_unsupported_Flags ) # ^
# the 04_2f subgroup uses the same encoding, but the areg is already used as sub-opcode select, so any modes relying on areg bits for other reasons (sign, condition) (modes 10, 11m0, 11m1) are illegal. the destination is also breg not areg
EmitGroup04(f, "04_2f_02", "LSR1", "UINT32 result = c >> 1;", "m_regs[breg] = result;","", 2,1, -1, EmitGroup04_Handle_NZC_LSR1_Flags ) # no alt handler (invalid path)
EmitGroup04(f, "04_2f_03", "ROR", "int shift = 1; UINT32 mask = (1 << (shift)) - 1; mask <<= (32-shift); UINT32 result = ((c >> shift) & ~mask) | ((c << (32-shift)) & mask);", "m_regs[breg] = result;","", 2,1, -1, EmitGroup04_Handle_NZC_LSR1_Flags )

# xxx_S c, b, u3 format opcodes (note c is destination)
EmitGroup0d(f, "0d_00", "ADD_S", "UINT32 result = m_regs[breg] + u;", "m_regs[creg] = result;" )
EmitGroup0d(f, "0d_01", "SUB_S", "UINT32 result = m_regs[breg] - u;", "m_regs[creg] = result;" )
EmitGroup0d(f, "0d_02", "ASL_S", "UINT32 result = m_regs[breg] << u;", "m_regs[creg] = result;" )

# xxx_S b <- b,c format opcodes (or in some cases xxx_S b,c)
EmitGroup0f(f, "0f_02", "SUB_S", "UINT32 result = m_regs[breg] - m_regs[creg];", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_04", "AND_S", "UINT32 result = m_regs[breg] & m_regs[creg];", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_05", "OR_S", "UINT32 result = m_regs[breg] | m_regs[creg];", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_07", "XOR_S", "UINT32 result = m_regs[breg] ^ m_regs[creg];", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_0f", "EXTB_S","UINT32 result = m_regs[creg] & 0x000000ff;", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_10", "EXTW_S","UINT32 result = m_regs[creg] & 0x0000ffff;", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_13", "NEG_S"," UINT32 result = 0 - m_regs[creg];", "m_regs[breg] = result;" )

EmitGroup0f(f, "0f_14", "ADD1_S"," UINT32 result = m_regs[breg] + (m_regs[creg] <<1);", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_15", "ADD2_S"," UINT32 result = m_regs[breg] + (m_regs[creg] <<2);", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_16", "ADD3_S"," UINT32 result = m_regs[breg] + (m_regs[creg] <<3);", "m_regs[breg] = result;" )
EmitGroup04(f, "04_2f_07", "EXTB", "UINT32 result = c & 0x000000ff;", "m_regs[breg] = result;","", 2,1, -1, EmitGroup04_unsupported_Flags ) # ^
EmitGroup04(f, "04_2f_08", "EXTW", "UINT32 result = c & 0x0000ffff;", "m_regs[breg] = result;","", 2,1, -1, EmitGroup04_unsupported_Flags ) # ^

EmitGroup0f(f, "0f_19", "LSR_S", "UINT32 result = m_regs[breg] >> (m_regs[creg]&0x1f);","m_regs[breg] = result;" )
EmitGroup0f(f, "0f_1b", "ASL1_S","UINT32 result = m_regs[creg] << 1;", "m_regs[breg] = result;" )
# xxx_S c, b, u3 format opcodes (note c is destination)
EmitGroup0d(f, "0d_00", "ADD_S", "UINT32 result = m_regs[breg] + u;", "m_regs[creg] = result;" )
EmitGroup0d(f, "0d_01", "SUB_S", "UINT32 result = m_regs[breg] - u;", "m_regs[creg] = result;" )
EmitGroup0d(f, "0d_02", "ASL_S", "UINT32 result = m_regs[breg] << u;", "m_regs[creg] = result;" )

# xxx_S b <- b,c format opcodes (or in some cases xxx_S b,c)
EmitGroup0f(f, "0f_02", "SUB_S", "UINT32 result = m_regs[breg] - m_regs[creg];", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_04", "AND_S", "UINT32 result = m_regs[breg] & m_regs[creg];", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_05", "OR_S", "UINT32 result = m_regs[breg] | m_regs[creg];", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_07", "XOR_S", "UINT32 result = m_regs[breg] ^ m_regs[creg];", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_0f", "EXTB_S","UINT32 result = m_regs[creg] & 0x000000ff;", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_10", "EXTW_S","UINT32 result = m_regs[creg] & 0x0000ffff;", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_13", "NEG_S"," UINT32 result = 0 - m_regs[creg];", "m_regs[breg] = result;" )

# xxx_S b, b, u5 format opcodes
EmitGroup17(f, "17_00", "ASL_S", "m_regs[breg] = m_regs[breg] << (u&0x1f);" )
EmitGroup17(f, "17_01", "LSR_S", "m_regs[breg] = m_regs[breg] >> (u&0x1f);" )
EmitGroup17(f, "17_02", "ASR_S", "INT32 temp = (INT32)m_regs[breg]; m_regs[breg] = temp >> (u&0x1f); // treat it as a signed value, so sign extension occurs during shift" )
EmitGroup17(f, "17_03", "SUB_S", "m_regs[breg] = m_regs[breg] - u;" )
EmitGroup17(f, "17_04", "BSET_S", "m_regs[breg] = m_regs[breg] | (1 << (u & 0x1f));" )

EmitGroup17(f, "17_06", "BMSK_S", "m_regs[breg] = m_regs[breg] | ((1 << (u + 1)) - 1);" )
EmitGroup0f(f, "0f_14", "ADD1_S"," UINT32 result = m_regs[breg] + (m_regs[creg] <<1);", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_15", "ADD2_S"," UINT32 result = m_regs[breg] + (m_regs[creg] <<2);", "m_regs[breg] = result;" )
EmitGroup0f(f, "0f_16", "ADD3_S"," UINT32 result = m_regs[breg] + (m_regs[creg] <<3);", "m_regs[breg] = result;" )

EmitGroup0f(f, "0f_19", "LSR_S", "UINT32 result = m_regs[breg] >> (m_regs[creg]&0x1f);","m_regs[breg] = result;" )
EmitGroup0f(f, "0f_1b", "ASL1_S","UINT32 result = m_regs[creg] << 1;", "m_regs[breg] = result;" )


# xxx_S b, b, u5 format opcodes
EmitGroup17(f, "17_00", "ASL_S", "m_regs[breg] = m_regs[breg] << (u&0x1f);" )
EmitGroup17(f, "17_01", "LSR_S", "m_regs[breg] = m_regs[breg] >> (u&0x1f);" )
EmitGroup17(f, "17_02", "ASR_S", "INT32 temp = (INT32)m_regs[breg]; m_regs[breg] = temp >> (u&0x1f); // treat it as a signed value, so sign extension occurs during shift" )
EmitGroup17(f, "17_03", "SUB_S", "m_regs[breg] = m_regs[breg] - u;" )
EmitGroup17(f, "17_04", "BSET_S", "m_regs[breg] = m_regs[breg] | (1 << (u & 0x1f));" )

EmitGroup17(f, "17_06", "BMSK_S", "m_regs[breg] = m_regs[breg] | ((1 << (u + 1)) - 1);" )

except Exception:
err = sys.exc_info()[1]
sys.stderr.write("cannot write file %s [%s]\n" % (sys.argv[1], err))
sys.exit(1)
97 changes: 47 additions & 50 deletions src/emu/cpu/h8/h8make.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -263,50 +263,49 @@ def __init__(self, fname, dtype):
self.dispatch = {}
self.macros = {}
try:
f = open(fname, "r")
with open(fname, "r") as f:
inf = None
for line in f:
if line.startswith("#"):
continue
line = line.rstrip()
if not line:
continue
if line.startswith(" ") or line.startswith("\t"):
if inf is not None:
# append instruction to last opcode, maybe expand a macro
tokens = line.split()
if tokens[0] in self.macros:
self.macros[tokens[0]].apply(inf, tokens)
else:
inf.add_source_line(line)
else:
# New opcode
tokens = line.split()
if tokens[0] == "macro":
inf = Macro(tokens)
self.macros[inf.name] = inf
elif len(tokens) == 2 or len(tokens) == 3:
if len(tokens) >= 3:
otype = name_to_type(tokens[2])
else:
otype = -1
inf = Special(tokens[0], tokens[1], otype, dtype)
self.states_info.append(inf)
else:
if len(tokens) >= 7:
otype = name_to_type(tokens[6])
else:
otype = -1
if otype == -1 or dtype == 0 or (otype != 0 and dtype != 0):
inf = Opcode(tokens[0], tokens[1], tokens[2], tokens[3], tokens[4], tokens[5], otype, dtype)
self.opcode_info.append(inf)
else:
inf = None
except Exception:
err = sys.exc_info()[1]
sys.stderr.write("Cannot read opcodes file %s [%s]\n" % (fname, err))
sys.exit(1)

inf = None
for line in f:
if line.startswith("#"):
continue
line = line.rstrip()
if not line:
continue
if line.startswith(" ") or line.startswith("\t"):
if inf is not None:
# append instruction to last opcode, maybe expand a macro
tokens = line.split()
if tokens[0] in self.macros:
self.macros[tokens[0]].apply(inf, tokens)
else:
inf.add_source_line(line)
else:
# New opcode
tokens = line.split()
if tokens[0] == "macro":
inf = Macro(tokens)
self.macros[inf.name] = inf
elif len(tokens) == 2 or len(tokens) == 3:
if len(tokens) >= 3:
otype = name_to_type(tokens[2])
else:
otype = -1
inf = Special(tokens[0], tokens[1], otype, dtype)
self.states_info.append(inf)
else:
if len(tokens) >= 7:
otype = name_to_type(tokens[6])
else:
otype = -1
if otype == -1 or dtype == 0 or (otype != 0 and dtype != 0):
inf = Opcode(tokens[0], tokens[1], tokens[2], tokens[3], tokens[4], tokens[5], otype, dtype)
self.opcode_info.append(inf)
else:
inf = None

def get(self, i):
if i in self.dispatch:
Expand Down Expand Up @@ -453,21 +452,19 @@ def main(argv):
opcodes = OpcodeList(argv[1], dtype)

try:
f = open(argv[3], "w")
with open(argv[3], "w") as f:
opcodes.build_dispatch()
opcodes.save_dasm(f, dname)
opcodes.save_opcodes(f, dname)
if dtype == 0:
opcodes.save_dispatch(f, dname)
opcodes.save_exec(f, dname, dtype, "full")
opcodes.save_exec(f, dname, dtype, "partial")
except Exception:
err = sys.exc_info()[1]
sys.stderr.write("cannot write file %s [%s]\n" % (argv[3], err))
sys.exit(1)

opcodes.build_dispatch()
opcodes.save_dasm(f, dname)
opcodes.save_opcodes(f, dname)
if dtype == 0:
opcodes.save_dispatch(f, dname)
opcodes.save_exec(f, dname, dtype, "full")
opcodes.save_exec(f, dname, dtype, "partial")
f.close()

# ======================================================================
if __name__ == "__main__":
sys.exit(main(sys.argv))
Expand Down
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