RISC-V---Datapath-and-Control-Logic

RISC V - Datapath and Control Logic

Structure of Datapath

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
BranchComp_ALU.v		BranchComp_ALU.v
ControlROM.txt		ControlROM.txt
DMEM.v		DMEM.v
Datapath.PNG		Datapath.PNG
IMEM.v		IMEM.v
ImmGen.v		ImmGen.v
LICENSE		LICENSE
PC.v		PC.v
README.md		README.md
REG.v		REG.v
Timing.PNG		Timing.PNG
Timing_ModelSim.PNG		Timing_ModelSim.PNG
control_logic.v		control_logic.v
modulePC.PNG		modulePC.PNG
moduleREG_ImmGen.PNG		moduleREG_ImmGen.PNG
module_BranchComp_ALU.PNG		module_BranchComp_ALU.PNG
module_Dmem.PNG		module_Dmem.PNG
tb.v		tb.v
testbench_IMEM.v		testbench_IMEM.v
testbench_REG.v		testbench_REG.v
testbench_datapath.v		testbench_datapath.v
top_datapath.v		top_datapath.v