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# created on:	07/21/2012 
# created by:	jwwebb
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#  Copyright (c) 2012, Jeremy W. Webb 
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Anyone who designs with Verilog HDL has probably grown tired of generating 
module instantiations in a hierarchical design, or creating a new top level 
or lower level Verilog HDL module. I have generated a few Perl Scripts that 
will automatically generate the module instantiations, top level module, and 
lower level module for you. These Perl Scripts can be invoked from within 
VI/VIM/GVIM, or a DOS Command Window. If you invoke them from within VI, the 
script output will be printed in the current file. If you invoke them from 
within a DOS, Cygwin, or Bash Command Window, then you will have to either 
cut and paste into your Verilog HDL file or pipe the output to a new file.

The company name in the header of each generated file can be customized during
the installation of the VerilogTools Perl Module. Each Perl script used
to generate Verilog modules will insert the custom company name in the 
header of the module.