added mem-init file and fixed imm_J,B formats

jstalex · Nov 20, 2022 · a4aed8d · a4aed8d
1 parent 6dff87d
commit a4aed8d
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Showing 9 changed files with 44 additions and 13 deletions.
diff --git a/aps_.ip_user_files/mem_init_files/mem-init.txt b/aps_.ip_user_files/mem_init_files/mem-init.txt
@@ -0,0 +1,10 @@
+00000001
+00000004
+00000005
+00000008
+0000000b
+00000003
+00000001
+00000004
+00000002
+00000007
diff --git a/aps_.ip_user_files/mem_init_files/prog.txt b/aps_.ip_user_files/mem_init_files/prog.txt
@@ -1,5 +1,4 @@
-10000417
-00040413
+00000413
 00000493
 00000913
 00a00a13

diff --git a/aps_.srcs/sim_1/new/top_tb.sv b/aps_.srcs/sim_1/new/top_tb.sv
@@ -17,7 +17,7 @@ cpu_top dut(.CLK100MHZ(CLK), .rst(rst));
 
 initial begin
   rst <= 1;
-  #10;
+  #20;
   rst <= 0;
 end
 

diff --git a/aps_.srcs/sources_1/new/cpu_top.sv b/aps_.srcs/sources_1/new/cpu_top.sv
@@ -53,19 +53,21 @@ logic [`WORD_LEN-1:0] imm_S;
 assign imm_S = {{(`WORD_LEN - 12) {instruction[31]}}, instruction[`S_TYPE_IMM_11_5], instruction[`S_TYPE_IMM_4_0]};
 
 logic [`WORD_LEN-1:0] imm_J;
-assign imm_J = {{(`WORD_LEN - 20) {instruction[31]}},
+assign imm_J = {{(`WORD_LEN - 21) {instruction[31]}},
     instruction[`J_TYPE_IMM_20],
     instruction[`J_TYPE_IMM_19_12],
     instruction[`J_TYPE_IMM_11],
-    instruction[`J_TYPE_IMM_10_1]
+    instruction[`J_TYPE_IMM_10_1],
+    1'b0
 };
 
 logic [`WORD_LEN-1:0] imm_B;
-assign imm_B = {{(`WORD_LEN - 12) {instruction[31]}}, 
+assign imm_B = {{(`WORD_LEN - 13) {instruction[31]}}, 
     instruction[`B_TYPE_IMM_12],
     instruction[`B_TYPE_IMM_11],
     instruction[`B_TYPE_IMM_10_5],
-    instruction[`B_TYPE_IMM_4_1]
+    instruction[`B_TYPE_IMM_4_1],
+    1'b0
 };
 
 // alu 

diff --git a/aps_.srcs/sources_1/new/data_memory.sv b/aps_.srcs/sources_1/new/data_memory.sv
@@ -12,6 +12,8 @@ module data_memory#(
     );
 
 logic [WIDTH-1:0] RAM [0:DEPTH-1];
+
+initial $readmemh("mem-init.txt", RAM, 0, DEPTH-1); 
 
 assign RD = RAM[A[9:2]];  
 

diff --git a/aps_.srcs/sources_1/new/defines_riscv.v b/aps_.srcs/sources_1/new/defines_riscv.v
@@ -201,7 +201,6 @@
 //I-type.4
 `define SYSTEM_OPCODE 5'b11_100
 
-//?
 `define MISC_MEM_OPCODE 5'b00_011
 
 //----------------------------//

diff --git a/aps_.srcs/sources_1/new/mem-init.txt b/aps_.srcs/sources_1/new/mem-init.txt
@@ -0,0 +1,10 @@
+00000001
+00000004
+00000005
+00000008
+0000000b
+00000003
+00000001
+00000004
+00000002
+00000007
diff --git a/aps_.srcs/sources_1/new/prog.txt b/aps_.srcs/sources_1/new/prog.txt
@@ -1,5 +1,4 @@
-10000417
-00040413
+00000413
 00000493
 00000913
 00a00a13

diff --git a/aps_.xpr b/aps_.xpr
@@ -32,7 +32,7 @@
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSAVendor" Val="xilinx"/>
     <Option Name="DSANumComputeUnits" Val="60"/>
-    <Option Name="WTXSimLaunchSim" Val="84"/>
+    <Option Name="WTXSimLaunchSim" Val="88"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -123,6 +123,12 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/new/mem-init.txt">
+        <FileInfo SFType="MIF">
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
         <Option Name="TopModule" Val="cpu_top"/>
@@ -222,7 +228,9 @@
   <Runs Version="1" Minor="10">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -231,7 +239,9 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
-Original file line number
+Diff line change
@@ Expand Up / @@ -17,7 +17,7 @@ cpu_top dut(.CLK100MHZ(CLK), .rst(rst)); @@
     initial begin
       rst <= 1;
-      #10;
+      #20;
       rst <= 0;
     end
@@ Expand Down @@