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Add additional regression tests for issue steveicarus#1099.
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module top; | ||
reg [3:0] inp1; | ||
reg signed [3:0] inp2; | ||
wire [4:0] out1, out2; | ||
initial begin | ||
$monitor("%b %b %b %b", inp1, inp2, out1, out2); | ||
#1 inp1 = 4'b1111; | ||
#1 inp2 = 4'b1111; | ||
#1; | ||
if ((out1 === 5'b01111) && (out2 === 5'b01111)) | ||
$display("PASSED"); | ||
else | ||
$display("FAILED"); | ||
end | ||
mod m1(inp1[3:0], out1); | ||
mod m2(inp2[3:0], out2); | ||
endmodule | ||
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||
module mod( | ||
input [4:0] inp, | ||
output [4:0] out | ||
); | ||
assign out = inp; | ||
endmodule |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,24 @@ | ||
module top; | ||
reg [3:0] inp1; | ||
reg signed [3:0] inp2; | ||
wire [4:0] out1, out2; | ||
initial begin | ||
$monitor("%b %b %b %b", inp1, inp2, out1, out2); | ||
#1 inp1 = 4'b1111; | ||
#1 inp2 = 4'b1111; | ||
#1; | ||
if ((out1 === 5'b01111) && (out2 === 5'b01111)) | ||
$display("PASSED"); | ||
else | ||
$display("FAILED"); | ||
end | ||
mod m1($unsigned(inp1), out1); | ||
mod m2($unsigned(inp2), out2); | ||
endmodule | ||
|
||
module mod( | ||
input [4:0] inp, | ||
output [4:0] out | ||
); | ||
assign out = inp; | ||
endmodule |
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{ | ||
"type" : "normal", | ||
"source" : "br_gh1099a.v" | ||
} |
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{ | ||
"type" : "normal", | ||
"source" : "br_gh1099b.v" | ||
} |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,4 @@ | ||
{ | ||
"type" : "normal", | ||
"source" : "br_gh1099c.v" | ||
} |