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First output formats' test was added; minor codestyle fixes.
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Muxianesty committed Aug 5, 2024
1 parent 310d312 commit 8a793dd
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Showing 9 changed files with 60 additions and 35 deletions.
1 change: 1 addition & 0 deletions test/model/dfcxx/CMakeLists.txt
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Expand Up @@ -6,5 +6,6 @@ set(DFCXX_TESTS
model/dfcxx/addconst.cpp
model/dfcxx/movingsum.cpp
model/dfcxx/idct.cpp
model/dfcxx/output_formats.cpp
PARENT_SCOPE
)
6 changes: 3 additions & 3 deletions test/model/dfcxx/addconst.cpp
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Expand Up @@ -16,15 +16,15 @@ static const DFOutputPaths nullDevicePath =
TEST(DFCxx, AddConstAddInt2Asap) {
AddConst kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2}
{dfcxx::ADD_INT, 2}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
}

TEST(DFCxx, AddConstAddInt2Linear) {
AddConst kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2}
{dfcxx::ADD_INT, 2}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
}
}
12 changes: 6 additions & 6 deletions test/model/dfcxx/idct.cpp
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Expand Up @@ -16,9 +16,9 @@ static const DFOutputPaths nullDevicePath =
TEST(DFCxx, IdctAsap) {
IDCT kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 1},
{dfcxx::MUL_INT, 3},
{dfcxx::SUB_INT, 1}
{dfcxx::ADD_INT, 1},
{dfcxx::MUL_INT, 3},
{dfcxx::SUB_INT, 1}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
}
Expand All @@ -28,9 +28,9 @@ TEST(DFCxx, IdctAsap) {
// TEST(DFCxx, IdctLinear) {
// IDCT kernel;
// DFLatencyConfig config = {
// {dfcxx::ADD_INT, 1},
// {dfcxx::MUL_INT, 3},
// {dfcxx::SUB_INT, 1}
// {dfcxx::ADD_INT, 1},
// {dfcxx::MUL_INT, 3},
// {dfcxx::SUB_INT, 1}
// };
// EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
// }
10 changes: 5 additions & 5 deletions test/model/dfcxx/matrixmul2.cpp
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Expand Up @@ -16,17 +16,17 @@ static const DFOutputPaths nullDevicePath =
TEST(DFCxx, MatrixMul2AddInt2MulInt3Asap) {
MatrixMul2 kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3},
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3},
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
}

TEST(DFCxx, MatrixMul2AddInt2MulInt3Linear) {
MatrixMul2 kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 2},
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 2},
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
}
}
10 changes: 5 additions & 5 deletions test/model/dfcxx/movingsum.cpp
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Expand Up @@ -16,31 +16,31 @@ static const DFOutputPaths nullDevicePath =
TEST(DFCxx, MovingSumAddInt2Asap) {
MovingSum kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2}
{dfcxx::ADD_INT, 2}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
}

TEST(DFCxx, MovingSumAddInt2Linear) {
MovingSum kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2}
{dfcxx::ADD_INT, 2}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
}

TEST(DFCxx, MovingSumAddInt8Asap) {
MovingSum kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 8}
{dfcxx::ADD_INT, 8}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
}

TEST(DFCxx, MovingSumAddInt8Linear) {
MovingSum kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 8}
{dfcxx::ADD_INT, 8}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
}
}
8 changes: 4 additions & 4 deletions test/model/dfcxx/muxmul.cpp
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Expand Up @@ -16,17 +16,17 @@ static const DFOutputPaths nullDevicePath =
TEST(DFCxx, MuxMulAddInt2MulInt3Asap) {
MuxMul kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
}

TEST(DFCxx, MuxMulAddInt2MulInt3Linear) {
MuxMul kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
}
24 changes: 24 additions & 0 deletions test/model/dfcxx/output_formats.cpp
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@@ -0,0 +1,24 @@
//===----------------------------------------------------------------------===//
//
// Part of the Utopia HLS Project, under the Apache License v2.0
// SPDX-License-Identifier: Apache-2.0
// Copyright 2021-2024 ISP RAS (http://www.ispras.ru)
//
//===----------------------------------------------------------------------===//

#include "polynomial2/polynomial2.h"

#include "gtest/gtest.h"

static const Polynomial2 kernel;

static const DFLatencyConfig config =
{{dfcxx::ADD_INT, 2}, {dfcxx::MUL_INT, 3}};

TEST(DFCxxOutputFormats, FIRRTL) {
Polynomial2 kernel;
DFOutputPaths paths = {
{dfcxx::OutputFormatID::SystemVerilog, NULLDEVICE}
};
EXPECT_EQ(kernel.compile(config, paths, dfcxx::ASAP), true);
}
16 changes: 8 additions & 8 deletions test/model/dfcxx/polynomial2.cpp
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Expand Up @@ -16,35 +16,35 @@ static const DFOutputPaths nullDevicePath =
TEST(DFCxx, Polynomial2AddInt2MulInt3Asap) {
Polynomial2 kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
}

TEST(DFCxx, Polynomial2AddInt2MulInt3Linear) {
Polynomial2 kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
}

TEST(DFCxx, Polynomial2AddInt8MulInt15Asap) {
Polynomial2 kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 8},
{dfcxx::MUL_INT, 15}
{dfcxx::ADD_INT, 8},
{dfcxx::MUL_INT, 15}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
}

TEST(DFCxx, Polynomial2AddInt8MulInt15Linear) {
Polynomial2 kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 8},
{dfcxx::MUL_INT, 15}
{dfcxx::ADD_INT, 8},
{dfcxx::MUL_INT, 15}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
}
8 changes: 4 additions & 4 deletions test/model/dfcxx/scalar3.cpp
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Expand Up @@ -16,17 +16,17 @@ static const DFOutputPaths nullDevicePath =
TEST(DFCxx, Scalar3AddInt2MulInt3Asap) {
Scalar3 kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::ASAP), true);
}

TEST(DFCxx, Scalar3AddInt2MulInt3Linear) {
Scalar3 kernel;
DFLatencyConfig config = {
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
{dfcxx::ADD_INT, 2},
{dfcxx::MUL_INT, 3}
};
EXPECT_EQ(kernel.compile(config, nullDevicePath, dfcxx::Linear), true);
}

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