refactor: rename functions

iscas-tis · Aug 22, 2024 · 86286d8 · 86286d8
1 parent a94000b
commit 86286d8
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Showing 3 changed files with 10 additions and 11 deletions.
diff --git a/src/main/scala/rvspeccore/checker/ArbitraryGenerater.scala b/src/main/scala/rvspeccore/checker/ArbitraryGenerater.scala
@@ -6,7 +6,7 @@ import chisel3.util.experimental.BoringUtils
 
 object ArbitraryRegFile {
   val uniqueIdArbitraryRegFile = "ArbitraryRegFile"
-  def genSink(implicit XLEN: Int): Vec[UInt] = {
+  def gen(implicit XLEN: Int): Vec[UInt] = {
     val initval = Wire(Vec(32, UInt(XLEN.W)))
     initval := DontCare
     BoringUtils.addSink(initval, uniqueIdArbitraryRegFile)

diff --git a/src/main/scala/rvspeccore/core/RiscvCore.scala b/src/main/scala/rvspeccore/core/RiscvCore.scala
@@ -7,7 +7,8 @@ import spec._
 import spec.instset.csr.CSR
 import spec.instset.csr.EventSig
 import spec.instset.csr.SatpStruct
-import rvspeccore.checker.ConnectCheckerResult
+
+import rvspeccore.checker.ArbitraryRegFile
 
 abstract class BaseCore()(implicit val config: RVConfig) extends Module {
   implicit val XLEN: Int = config.XLEN
@@ -77,10 +78,8 @@ object State {
     val state = Wire(new State)
 
     state.reg := {
-      if (config.formal.arbitraryRegFile)
-        rvspeccore.checker.ArbitraryRegFile.genSink
-      else
-        Seq.fill(32)(0.U(XLEN.W))
+      if (config.formal.arbitraryRegFile) ArbitraryRegFile.gen
+      else Seq.fill(32)(0.U(XLEN.W))
     }
     state.pc  := config.initValue.getOrElse("pc", "h8000_0000").U(XLEN.W)
     state.csr := CSR.wireInit()

diff --git a/src/test/scala/rvspeccore/checker/ArbitraryGeneraterSpec.scala b/src/test/scala/rvspeccore/checker/ArbitraryGeneraterSpec.scala
@@ -10,12 +10,14 @@ class TestArbitraryRegFileModule(hasBug: Boolean) extends Module {
   val io = IO(new Bundle {
     val rf = Output(Vec(32, UInt(64.W)))
   })
-  io.rf := ArbitraryRegFile.genSink
+  io.rf := ArbitraryRegFile.gen
   ArbitraryRegFile.init
 
-  if (hasBug)
+  if (hasBug) {
+    // this assertion should fail because the rf(1) is arbitrary, could be not 0.U
+    // will print a "Assertion failed"
     assert(io.rf(1) === 0.U)
-  else
+  } else
     assert(io.rf(0) === 0.U)
 }
 
@@ -24,8 +26,6 @@ class ArbitraryRegFileSpec extends AnyFlatSpec with Formal with ChiselScalatestT
   it should "be able to create arbitrary regFile init value" in {
     verify(new TestArbitraryRegFileModule(false), Seq(BoundedCheck(2), BtormcEngineAnnotation))
     assertThrows[chiseltest.formal.FailedBoundedCheckException] {
-      // fail because the rf(1) is Arbitrary, could be not 0.U
-      // this will print a "Assertion failed at ArbitraryGeneraterSpec.scala:17 assert(io.rf(1) === 0.U)"
       verify(new TestArbitraryRegFileModule(true), Seq(BoundedCheck(2), BtormcEngineAnnotation))
     }
   }