feat: use CHA

iscas-tis · Nov 27, 2023 · 15a1717 · 15a1717
1 parent dce1504
commit 15a1717
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Showing 4 changed files with 10 additions and 11 deletions.
diff --git a/build.sbt b/build.sbt
@@ -33,14 +33,14 @@ lazy val root = (project in file("."))
   .settings(
     name := "RiscvSpecCore",
     libraryDependencies ++= Seq(
-      "edu.berkeley.cs" %% "chisel3"    % "3.6.0",
-      "edu.berkeley.cs" %% "chiseltest" % "0.6.2" % "test"
+      "cn.ac.ios.tis" %% "chisel3"    % "3.7-SNAPSHOT",
+      "cn.ac.ios.tis" %% "chiseltest" % "0.7-SNAPSHOT" % "test"
     ),
     scalacOptions ++= Seq(
       "-language:reflectiveCalls",
       "-deprecation",
       "-feature",
       "-Xcheckinit"
     ),
-    addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.6.0" cross CrossVersion.full)
+    addCompilerPlugin("cn.ac.ios.tis" % "chisel3-plugin" % "3.7-SNAPSHOT" cross CrossVersion.full)
   )
diff --git a/src/main/scala/rvspeccore/core/spec/instset/IBase.scala b/src/main/scala/rvspeccore/core/spec/instset/IBase.scala
@@ -128,7 +128,7 @@ trait IBase extends BaseCore with CommonDecode with IBaseInsts with ExceptionSup
 
   }
   def addrAligned(size: UInt, addr: UInt): Bool = {
-      MuxLookup(size, false.B)(
+      MuxLookup(size, false.B,
         Seq(
           "b00".U   -> true.B,              //b
           "b01".U   -> (addr(0)   === 0.U), //h
@@ -161,8 +161,7 @@ trait IBase extends BaseCore with CommonDecode with IBaseInsts with ExceptionSup
   def getfetchSize():UInt = {
     MuxLookup(
       now.csr.misa(CSR.getMisaExtInt('C')),
-      SizeOp.w
-    )(
+      SizeOp.w,
       Seq(
         "b0".U   -> SizeOp.w,
         "b1".U   -> SizeOp.h

diff --git a/src/main/scala/rvspeccore/core/spec/instset/ZicsrExtension.scala b/src/main/scala/rvspeccore/core/spec/instset/ZicsrExtension.scala
@@ -53,7 +53,7 @@ trait ZicsrExtension extends BaseCore with CommonDecode with ZicsrExtensionInsts
     val isIllegalMode  = priviledgeMode < addr(9, 8)
     // val isIllegalWrite = wen && (addr(11, 10) === "b11".U) && !justRead  // Write a read-only CSR register
     val isIllegalAccess = isIllegalMode || isIllegalWrite
-    val has:       Bool = MuxLookup(addr, false.B)(now.csr.table.map { x => x.info.addr -> true.B })
+    val has:       Bool = MuxLookup(addr, false.B, now.csr.table.map { x => x.info.addr -> true.B })
     when(isIllegalAccess || !has) {
       raiseException(MExceptionCode.illegalInstruction)
     }

diff --git a/src/main/scala/rvspeccore/core/spec/instset/csr/CSRSupport.scala b/src/main/scala/rvspeccore/core/spec/instset/csr/CSRSupport.scala
@@ -21,9 +21,9 @@ trait CSRSupport extends BaseCore with ExceptionSupport {
     // Read the value of special registers
     // CSR addr require 12bit
     require(addr.getWidth == 12)
-    val has:    Bool = MuxLookup(addr, false.B)(now.csr.table.map { x => x.info.addr -> true.B })
-    val nowCSR: UInt = MuxLookup(addr, 0.U)(now.csr.table.map { x => x.info.addr -> x.signal })
-    val rmask:  UInt = MuxLookup(addr, 0.U)(now.csr.table.map { x => x.info.addr -> x.info.rmask })
+    val has:    Bool = MuxLookup(addr, false.B, now.csr.table.map { x => x.info.addr -> true.B })
+    val nowCSR: UInt = MuxLookup(addr, 0.U, now.csr.table.map { x => x.info.addr -> x.signal })
+    val rmask:  UInt = MuxLookup(addr, 0.U, now.csr.table.map { x => x.info.addr -> x.info.rmask })
     printf("[Debug]CSR_READ:(Have:%d, nowCSR:%x, Addr: %x %x)\n",has,nowCSR,addr,next.reg(1))
     val rData = WireInit(0.U(XLEN.W))
 
@@ -59,7 +59,7 @@ trait CSRSupport extends BaseCore with ExceptionSupport {
   def csrWrite(addr: UInt, data: UInt): Unit = {
     def UnwritableMask = 0.U(XLEN.W)
     require(addr.getWidth == 12)
-    val has: Bool = MuxLookup(addr, false.B)(now.csr.table.map { x => x.info.addr -> true.B })
+    val has: Bool = MuxLookup(addr, false.B, now.csr.table.map { x => x.info.addr -> true.B })
     when(has) {
       // require(mask.getWidth == XLEN)
       // common wirte