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fix VM event grouping issues (#48)
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@hsane2001
hsane2001 authored Aug 8, 2023
1 parent adef7bd commit 1821112
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Showing 12 changed files with 165 additions and 154 deletions.
1 change: 0 additions & 1 deletion Makefile
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Expand Up @@ -58,7 +58,6 @@ dist/$(PACKAGE_EXTERNAL): build_dir build/libtsc build-public/collect build-publ
cp build/$(BINARY_COLLECT) dist/$(BINARY_FINAL)/$(BINARY_COLLECT)
cp build/$(BINARY_POSTPROCESS) dist/$(BINARY_FINAL)/$(BINARY_POSTPROCESS)
cp LICENSE dist/$(BINARY_FINAL)/
cp README.md dist/$(BINARY_FINAL)/README.md
cd dist && tar -czf $(PACKAGE_EXTERNAL) $(BINARY_FINAL)
cd dist && cp -r $(BINARY_FINAL) ../build/
rm -rf dist/$(BINARY_FINAL)/
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2 changes: 1 addition & 1 deletion README.md
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Expand Up @@ -90,4 +90,4 @@ Requires recent python. On successful build, binaries will be created in `dist`
```
pip3 install -r requirements.txt
make
```
```
2 changes: 1 addition & 1 deletion _version.txt
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@@ -1 +1 @@
1.3.3
1.3.4
4 changes: 1 addition & 3 deletions events/bdx.txt
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Expand Up @@ -3,8 +3,7 @@
# SPDX-License-Identifier: BSD-3-Clause
###########################################################################################################

# Broadwell event list (default, with extensive TMA collection)

# Broadwell event list
cpu/event=0xc2,umask=0x02,period=2000003,name='UOPS_RETIRED.RETIRE_SLOTS'/,
cpu/event=0xc5,umask=0x00,name='BR_MISP_RETIRED.ALL_BRANCHES'/,
cpu/event=0xc3,umask=0x01,name='MACHINE_CLEARS.COUNT'/,
Expand Down Expand Up @@ -173,4 +172,3 @@ imc/event=0x04,umask=0x0c,name='UNC_M_CAS_COUNT.WR'/;
#power related
power/energy-pkg/,
power/energy-ram/;

5 changes: 2 additions & 3 deletions events/clx_skx.txt
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Expand Up @@ -3,8 +3,7 @@
# SPDX-License-Identifier: BSD-3-Clause
###########################################################################################################

# Cascadelake event list (default, with extensive TMA collection)

# Cascadelake event list
#avx related power levels
cpu/event=0x28,umask=0x07,period=200003,name='CORE_POWER.LVL0_TURBO_LICENSE'/,
cpu/event=0x28,umask=0x18,period=200003,name='CORE_POWER.LVL1_TURBO_LICENSE'/,
Expand Down Expand Up @@ -239,4 +238,4 @@ iio/event=0x83,umask=0x01,ch_mask=0x08,fc_mask=0x07,name='UNC_IIO_DATA_REQ_OF_CP
upi/event=0x2,umask=0x0f,name='UNC_UPI_TxL_FLITS.ALL_DATA'/,
upi/event=0x2,umask=0x97,name='UNC_UPI_TxL_FLITS.NON_DATA'/,
upi/event=0x1,umask=0x0,name='UNC_UPI_CLOCKTICKS'/,
upi/event=0x21,umask=0x0,name='UNC_UPI_L1_POWER_CYCLES'/;
upi/event=0x21,umask=0x0,name='UNC_UPI_L1_POWER_CYCLES'/;
2 changes: 1 addition & 1 deletion events/icx.txt
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Expand Up @@ -3,7 +3,7 @@
# SPDX-License-Identifier: BSD-3-Clause
###########################################################################################################

# Icelake event list (default)
# Icelake event list
cpu/event=0x51,umask=0x01,period=100003,name='L1D.REPLACEMENT'/,
cpu/event=0xd1,umask=0x01,period=1000003,name='MEM_LOAD_RETIRED.L1_HIT'/,
cpu/event=0x24,umask=0xe4,period=200003,name='L2_RQSTS.ALL_CODE_RD'/,
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4 changes: 2 additions & 2 deletions events/metric_bdx.json
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Expand Up @@ -29,7 +29,7 @@
"name": "metric_locks retired per instr",
"name-txn": "metric_locks retired per txn",
"expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [instructions]",
"expression-txn": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]",
"expression-txn": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]",
"origin": "perfmon website"
},
{
Expand Down Expand Up @@ -386,4 +386,4 @@
"expression": "100 * (([UOPS_RETIRED.RETIRE_SLOTS] / [UOPS_ISSUED.ANY]) * [IDQ.MS_UOPS] )/ (4 * ([CPU_CLK_UNHALTED.THREAD_ANY] / [const_thread_count]))",
"origin": "perfspect"
}
]
]
78 changes: 39 additions & 39 deletions events/metric_icx.json
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Expand Up @@ -14,22 +14,22 @@
},
{
"name": "metric_CPI",
"name-txn": "metric_cycles per txn",
"name-txn": "metric_cycles per txn",
"expression": "[cpu-cycles] / [instructions]",
"expression-txn": "[cpu-cycles] / [TXN]"
"expression-txn": "[cpu-cycles] / [TXN]"
},
{
"name": "metric_kernel_CPI",
"name-txn": "metric_kernel_cycles per txn",
"name-txn": "metric_kernel_cycles per txn",
"expression": "[cpu-cycles:k] / [instructions:k]",
"expression-txn": "[cpu-cycles:k] / [TXN]",
"expression-txn": "[cpu-cycles:k] / [TXN]",
"origin": "perfspect"
},
{
"name": "metric_IPC",
"name-txn": "metric_txn per cycles",
"name-txn": "metric_txn per cycles",
"expression": "[instructions] / [cpu-cycles]",
"expression-txn": "[instructions] / [TXN]",
"expression-txn": "[instructions] / [TXN]",
"origin": "perfspect"
},
{
Expand All @@ -39,52 +39,52 @@
},
{
"name": "metric_locks retired per instr",
"name-txn": "metric_locks retired per txn",
"name-txn": "metric_locks retired per txn",
"expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [instructions]",
"expression-txn": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]",
"expression-txn": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]",
"origin": "perfmon website"
},
{
"name": "metric_L1D MPI (includes data+rfo w/ prefetches)",
"name-txn": "metric_L1D misses per txn (includes data+rfo w/ prefetches)",
"name-txn": "metric_L1D misses per txn (includes data+rfo w/ prefetches)",
"expression": "[L1D.REPLACEMENT] / [instructions]",
"expression-txn": "[L1D.REPLACEMENT] / [TXN]"
"expression-txn": "[L1D.REPLACEMENT] / [TXN]"
},
{
"name": "metric_L1D demand data read hits per instr",
"name-txn": "metric_L1D demand data read hits per txn",
"name-txn": "metric_L1D demand data read hits per txn",
"expression": "[MEM_LOAD_RETIRED.L1_HIT] / [instructions]",
"expression-txn": "[MEM_LOAD_RETIRED.L1_HIT] / [TXN]"
"expression-txn": "[MEM_LOAD_RETIRED.L1_HIT] / [TXN]"
},
{
"name": "metric_L1-I code read misses (w/ prefetches) per instr",
"name-txn": "metric_L1I code read misses (includes prefetches) per txn",
"name-txn": "metric_L1I code read misses (includes prefetches) per txn",
"expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]",
"expression-txn": "[L2_RQSTS.ALL_CODE_RD] / [TXN]"
"expression-txn": "[L2_RQSTS.ALL_CODE_RD] / [TXN]"
},
{
"name": "metric_L2 demand data read hits per instr",
"name-txn": "metric_L2 demand data read hits per txn",
"name-txn": "metric_L2 demand data read hits per txn",
"expression": "[MEM_LOAD_RETIRED.L2_HIT] / [instructions]",
"expression-txn": "[MEM_LOAD_RETIRED.L2_HIT] / [TXN]"
"expression-txn": "[MEM_LOAD_RETIRED.L2_HIT] / [TXN]"
},
{
"name": "metric_L2 MPI (includes code+data+rfo w/ prefetches)",
"name-txn": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)",
"name-txn": "metric_L2 misses per txn (includes code+data+rfo w/ prefetches)",
"expression": "[L2_LINES_IN.ALL] / [instructions]",
"expression-txn": "[L2_LINES_IN.ALL] / [TXN]"
"expression-txn": "[L2_LINES_IN.ALL] / [TXN]"
},
{
"name": "metric_L2 demand data read MPI",
"name-txn": "metric_L2 demand data read misses per txn",
"name-txn": "metric_L2 demand data read misses per txn",
"expression": "[MEM_LOAD_RETIRED.L2_MISS] / [instructions]",
"expression-txn": "[MEM_LOAD_RETIRED.L2_MISS] / [TXN]"
"expression-txn": "[MEM_LOAD_RETIRED.L2_MISS] / [TXN]"
},
{
"name": "metric_L2 demand code MPI",
"name-txn": "metric_L2 demand code misses per txn",
"name-txn": "metric_L2 demand code misses per txn",
"expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]",
"expression-txn": "[L2_RQSTS.CODE_RD_MISS] / [TXN]"
"expression-txn": "[L2_RQSTS.CODE_RD_MISS] / [TXN]"
},
{
"name": "metric_Average LLC data read miss latency (in clks)",
Expand Down Expand Up @@ -160,27 +160,27 @@
},
{
"name": "metric_LLC code read MPI (demand+prefetch)",
"name-txn": "metric_LLC code read (demand+prefetch) misses per txn",
"name-txn": "metric_LLC code read (demand+prefetch) misses per txn",
"expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_CRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF]) / [instructions]",
"expression-txn": "([UNC_CHA_TOR_INSERTS.IA_MISS_CRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF]) / [TXN]"
"expression-txn": "([UNC_CHA_TOR_INSERTS.IA_MISS_CRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF]) / [TXN]"
},
{
"name": "metric_LLC data read MPI (demand+prefetch)",
"name-txn": "metric_LLC data read (demand+prefetch) misses per txn",
"name-txn": "metric_LLC data read (demand+prefetch) misses per txn",
"expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [instructions]",
"expression-txn": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [TXN]"
"expression-txn": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [TXN]"
},
{
"name": "metric_LLC total HITM (per instr) (excludes LLC prefetches)",
"name-txn": "metric_LLC total HITM per txn (excludes LLC prefetches)",
"name-txn": "metric_LLC total HITM per txn (excludes LLC prefetches)",
"expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [instructions]",
"expression-txn": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [TXN]"
"expression-txn": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [TXN]"
},
{
"name": "metric_LLC total HIT clean line forwards (per instr) (excludes LLC prefetches)",
"name-txn": "metric_LLC total HIT clean line forwards per txn (excludes LLC prefetches)",
"name-txn": "metric_LLC total HIT clean line forwards per txn (excludes LLC prefetches)",
"expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [instructions]",
"expression-txn": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [TXN]"
"expression-txn": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [TXN]"
},
{
"name": "metric_Average LLC demand data read miss latency (in ns)",
Expand All @@ -196,27 +196,27 @@
},
{
"name": "metric_ITLB (2nd level) MPI",
"name-txn": "metric_ITLB (2nd level) misses per txn",
"name-txn": "metric_ITLB (2nd level) misses per txn",
"expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]",
"expression-txn": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]"
"expression-txn": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]"
},
{
"name": "metric_DTLB (2nd level) load MPI",
"name-txn": "metric_DTLB (2nd level) load misses per txn",
"name-txn": "metric_DTLB (2nd level) load misses per txn",
"expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]",
"expression-txn": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]"
"expression-txn": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]"
},
{
"name": "metric_DTLB (2nd level) 2MB large page load MPI",
"name-txn": "metric_DTLB (2nd level) 2MB large page load misses per txn",
"name-txn": "metric_DTLB (2nd level) 2MB large page load misses per txn",
"expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [instructions]",
"expression-txn": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [TXN]"
"expression-txn": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [TXN]"
},
{
"name": "metric_DTLB (2nd level) store MPI",
"name-txn": "metric_DTLB (2nd level) store misses per txn",
"name-txn": "metric_DTLB (2nd level) store misses per txn",
"expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]",
"expression-txn": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]"
"expression-txn": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]"
},
{
"name": "metric_NUMA %_Reads addressed to local DRAM",
Expand Down Expand Up @@ -394,4 +394,4 @@
"name": "metric_TMA_Info_System_SMT_2T_Utilization",
"expression": "1 - [CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE] / [CPU_CLK_UNHALTED.REF_DISTRIBUTED] if [SOCKET_COUNT] > 1 else 0"
}
]
]
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