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# Example Makefile | ||
# | ||
# Exercise 2, TDT4258 | ||
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CC=arm-none-eabi-gcc | ||
LD=arm-none-eabi-gcc | ||
OBJCOPY=arm-none-eabi-objcopy | ||
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CFLAGS=-mcpu=cortex-m3 -mthumb -g -std=c99 -Wall | ||
LDFLAGS=-mcpu=cortex-m3 -mthumb -g -lgcc -lc -lcs3 -lcs3unhosted -lefm32gg -Llib | ||
ASFLAGS=-mcpu=cortex-m3 -mthumb -g | ||
LINKERSCRIPT=lib/efm32gg.ld | ||
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ex2.bin : ex2.elf | ||
${OBJCOPY} -O binary $< $@ | ||
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ex2.elf : ex2.o timer.o dac.o gpio.o interrupt_handlers.o | ||
${LD} -T ${LINKERSCRIPT} $^ -o $@ ${LDFLAGS} | ||
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%.o : %.c | ||
${CC} ${CFLAGS} -c $< -o $@ | ||
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.PHONY : upload | ||
upload : | ||
-eACommander.sh -r --address 0x00000000 -f "ex2.bin" -r | ||
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.PHONY : clean | ||
clean : | ||
-rm -rf *.o *.elf *.bin *.hex |
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#include <stdint.h> | ||
#include <stdbool.h> | ||
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#include "efm32gg.h" | ||
#include "ex2.h" | ||
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void setupDAC() | ||
{ | ||
/* | ||
TODO enable and set up the Digital-Analog Converter | ||
1. Enable the DAC clock by setting bit 17 in CMU_HFPERCLKEN0 | ||
2. Prescale DAC clock by writing 0x50010 to DAC0_CTRL | ||
3. Enable left and right audio channels by writing 1 to DAC0_CH0CTRL and DAC0_CH1CTRL | ||
4. Write a continuous stream of samples to the DAC data registers, DAC0_CH0DATA and DAC0_CH1DATA, for example from a timer interrupt | ||
*/ | ||
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*CMU_HFPERCLKEN0 |= CMU2_HFPERCLKEN0_DAC0; | ||
*DAC0_CTRL = 0x50010; | ||
*DAC0_CH0CTRL = 1; | ||
*DAC0_CH1CTRL = 1; | ||
} |
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#include <stdint.h> | ||
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// GPIO | ||
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#define GPIO_PA_BASE 0x40006000 | ||
#define GPIO_PB_BASE 0x40006024 | ||
#define GPIO_PC_BASE 0x40006048 | ||
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#define GPIO_PA_CTRL ((volatile uint32_t*)(GPIO_PA_BASE + 0x00)) | ||
#define GPIO_PA_MODEL ((volatile uint32_t*)(GPIO_PA_BASE + 0x04)) | ||
#define GPIO_PA_MODEH ((volatile uint32_t*)(GPIO_PA_BASE + 0x08)) | ||
#define GPIO_PA_DOUT ((volatile uint32_t*)(GPIO_PA_BASE + 0x0c)) | ||
#define GPIO_PA_DOUTSET ((volatile uint32_t*)(GPIO_PA_BASE + 0x10)) | ||
#define GPIO_PA_DOUTCLR ((volatile uint32_t*)(GPIO_PA_BASE + 0x14)) | ||
#define GPIO_PA_DOUTTGL ((volatile uint32_t*)(GPIO_PA_BASE + 0x18)) | ||
#define GPIO_PA_DIN ((volatile uint32_t*)(GPIO_PA_BASE + 0x1c)) | ||
#define GPIO_PA_PINLOCKN ((volatile uint32_t*)(GPIO_PA_BASE + 0x20)) | ||
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#define GPIO_PB_CTRL ((volatile uint32_t*)(GPIO_PB_BASE + 0x00)) | ||
#define GPIO_PB_MODEL ((volatile uint32_t*)(GPIO_PB_BASE + 0x04)) | ||
#define GPIO_PB_MODEH ((volatile uint32_t*)(GPIO_PB_BASE + 0x08)) | ||
#define GPIO_PB_DOUT ((volatile uint32_t*)(GPIO_PB_BASE + 0x0c)) | ||
#define GPIO_PB_DOUTSET ((volatile uint32_t*)(GPIO_PB_BASE + 0x10)) | ||
#define GPIO_PB_DOUTCLR ((volatile uint32_t*)(GPIO_PB_BASE + 0x14)) | ||
#define GPIO_PB_DOUTTGL ((volatile uint32_t*)(GPIO_PB_BASE + 0x18)) | ||
#define GPIO_PB_DIN ((volatile uint32_t*)(GPIO_PB_BASE + 0x1c)) | ||
#define GPIO_PB_PINLOCKN ((volatile uint32_t*)(GPIO_PB_BASE + 0x20)) | ||
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#define GPIO_PC_CTRL ((volatile uint32_t*)(GPIO_PC_BASE + 0x00)) | ||
#define GPIO_PC_MODEL ((volatile uint32_t*)(GPIO_PC_BASE + 0x04)) | ||
#define GPIO_PC_MODEH ((volatile uint32_t*)(GPIO_PC_BASE + 0x08)) | ||
#define GPIO_PC_DOUT ((volatile uint32_t*)(GPIO_PC_BASE + 0x0c)) | ||
#define GPIO_PC_DOUTSET ((volatile uint32_t*)(GPIO_PC_BASE + 0x10)) | ||
#define GPIO_PC_DOUTCLR ((volatile uint32_t*)(GPIO_PC_BASE + 0x14)) | ||
#define GPIO_PC_DOUTTGL ((volatile uint32_t*)(GPIO_PC_BASE + 0x18)) | ||
#define GPIO_PC_DIN ((volatile uint32_t*)(GPIO_PC_BASE + 0x1c)) | ||
#define GPIO_PC_PINLOCKN ((volatile uint32_t*)(GPIO_PC_BASE + 0x20)) | ||
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#define GPIO_EXTIPSELL ((volatile uint32_t*)(GPIO_PA_BASE + 0x100)) | ||
#define GPIO_EXTIPSELH ((volatile uint32_t*)(GPIO_PA_BASE + 0x104)) | ||
#define GPIO_EXTIRISE ((volatile uint32_t*)(GPIO_PA_BASE + 0x108)) | ||
#define GPIO_EXTIFALL ((volatile uint32_t*)(GPIO_PA_BASE + 0x10c)) | ||
#define GPIO_IEN ((volatile uint32_t*)(GPIO_PA_BASE + 0x110)) | ||
#define GPIO_IFC ((volatile uint32_t*)(GPIO_PA_BASE + 0x11c)) | ||
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// CMU | ||
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#define CMU_BASE2 0x400c8000 | ||
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#define CMU_HFPERCLKDIV ((volatile uint32_t*)(CMU_BASE2 + 0x008)) | ||
#define CMU_HFCORECLKEN0 ((volatile uint32_t*)(CMU_BASE2 + 0x040)) | ||
#define CMU_HFPERCLKEN0 ((volatile uint32_t*)(CMU_BASE2 + 0x044)) | ||
#define CMU_CMD ((volatile uint32_t*)(CMU_BASE2 + 0x024)) | ||
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#define CMU2_HFPERCLKEN0_DAC0 (1 << 17) | ||
#define CMU2_HFPERCLKEN0_PRS (1 << 15) | ||
#define CMU2_HFPERCLKEN0_GPIO (1 << 13) | ||
#define CMU2_HFPERCLKEN0_TIMER1 (1 << 6) | ||
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#define CMU_HFCORECLKEN0_DMA (1 << 0) | ||
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// TIMER1 | ||
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#define TIMER1_BASE 0x40010400 | ||
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#define TIMER1_CMD ((volatile uint32_t*)(TIMER1_BASE + 0x04)) | ||
#define TIMER1_IEN ((volatile uint32_t*)(TIMER1_BASE + 0x0c)) | ||
#define TIMER1_IFC ((volatile uint32_t*)(TIMER1_BASE + 0x18)) | ||
#define TIMER1_TOP ((volatile uint32_t*)(TIMER1_BASE + 0x1c)) | ||
#define TIMER1_CNT ((volatile uint32_t*)(TIMER1_BASE + 0x24)) | ||
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// NVIC | ||
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#define ISER0 ((volatile uint32_t*)0xe000e100) | ||
#define ISER1 ((volatile uint32_t*)0xe000e104) | ||
#define ICER0 ((volatile uint32_t*)0xe000e180) | ||
#define ICER1 ((volatile uint32_t*)0xe000e184) | ||
#define ISPR0 ((volatile uint32_t*)0xe000e200) | ||
#define ISPR1 ((volatile uint32_t*)0xe000e204) | ||
#define ICPR0 ((volatile uint32_t*)0xe000e280) | ||
#define ICPR1 ((volatile uint32_t*)0xe000e284) | ||
#define IABR0 ((volatile uint32_t*)0xe000e300) | ||
#define IABR1 ((volatile uint32_t*)0xe000e304) | ||
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// IPR | ||
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#define IPR_BASE 0xe000e400 | ||
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#define IPR0 ((volatile uint32_t*)(IPR_BASE + 0x00)) | ||
#define IPR1 ((volatile uint32_t*)(IPR_BASE + 0x04)) | ||
#define IPR2 ((volatile uint32_t*)(IPR_BASE + 0x08)) | ||
#define IPR3 ((volatile uint32_t*)(IPR_BASE + 0x0c)) | ||
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// EMU | ||
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#define EMU_BASE2 0x400c6000 | ||
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#define EMU_CTRL ((volatile uint32_t*)(EMU_BASE2 + 0x000)) | ||
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// DAC0 | ||
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#define DAC0_BASE2 0x40004000 | ||
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#define DAC0_CTRL ((volatile uint32_t*)(DAC0_BASE2 + 0x000)) | ||
#define DAC0_CH0CTRL ((volatile uint32_t*)(DAC0_BASE2 + 0x008)) | ||
#define DAC0_CH1CTRL ((volatile uint32_t*)(DAC0_BASE2 + 0x00c)) | ||
#define DAC0_IEN ((volatile uint32_t*)(DAC0_BASE2 + 0x010)) | ||
#define DAC0_IF ((volatile uint32_t*)(DAC0_BASE2 + 0x014)) | ||
#define DAC0_IFS ((volatile uint32_t*)(DAC0_BASE2 + 0x018)) | ||
#define DAC0_IFC ((volatile uint32_t*)(DAC0_BASE2 + 0x01c)) | ||
#define DAC0_CH0DATA ((volatile uint32_t*)(DAC0_BASE2 + 0x020)) | ||
#define DAC0_CH1DATA ((volatile uint32_t*)(DAC0_BASE2 + 0x024)) | ||
#define DAC0_COMBDATA ((volatile uint32_t*)(DAC0_BASE2 + 0x028)) | ||
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// DMA | ||
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#define DMA_BASE 0x400c2000 | ||
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#define DMA_STATUS ((volatile uint32_t*)(DMA_BASE + 0x0000)) | ||
#define DMA_CONFIG ((volatile uint32_t*)(DMA_BASE + 0x0004)) | ||
#define DMA_CTRLBASE ((volatile uint32_t*)(DMA_BASE + 0x0008)) | ||
#define DMA_ALTCTRLBASE ((volatile uint32_t*)(DMA_BASE + 0x000c)) | ||
#define DMA_CHUSEBURSTS ((volatile uint32_t*)(DMA_BASE + 0x0018)) | ||
#define DMA_CHUSEBURSTC ((volatile uint32_t*)(DMA_BASE + 0x001c)) | ||
#define DMA_REQMASKC ((volatile uint32_t*)(DMA_BASE + 0x0024)) | ||
#define DMA_CHENS ((volatile uint32_t*)(DMA_BASE + 0x0028)) | ||
#define DMA_CHALTC ((volatile uint32_t*)(DMA_BASE + 0x0034)) | ||
#define DMA_IFC ((volatile uint32_t*)(DMA_BASE + 0x1008)) | ||
#define DMA_IEN ((volatile uint32_t*)(DMA_BASE + 0x100c)) | ||
#define DMA_CH0_CTRL ((volatile uint32_t*)(DMA_BASE + 0x1100)) | ||
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// PRS | ||
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#define PRS_BASE 0x400cc000 | ||
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#define PRS_CH0_CTRL ((volatile uint32_t*)(PRS_BASE + 0x010)) | ||
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// System Control Block | ||
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#define SCR ((volatile uint32_t*)0xe000ed10) | ||
#define SYSTICK_CTRL ((volatile uint32_t*)0xe000e010) | ||
#define SYSTICK_LOAD ((volatile uint32_t*)0xe000e014) | ||
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