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Create instructiondecoder.v
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Jag-M authored Aug 9, 2024
1 parent 426fcb4 commit b1593f6
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16 changes: 16 additions & 0 deletions rtl/50_core/instructiondecoder.v
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module instruction_decoder (
input [31:0] instr,
output reg [6:0] opcode,
output reg [4:0] rd, rs1, rs2,
output reg [2:0] funct3,
output reg [6:0] funct7
);
always @(*) begin
opcode = instr[6:0];
rd = instr[11:7];
rs1 = instr[19:15];
rs2 = instr[24:20];
funct3 = instr[14:12];
funct7 = instr[31:25];
end
endmodule

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