Add open-source FPGA cores (OpenFPGA/SOFA)

openfpga/sofa-chd.core

@@ -0,0 +1,20 @@
+CAPI=2:
+
+name: openfpga:cores:sofa-chd:1.0
+description: Hard-IP 12x12 FPGA core, Skywater Open-source FpgA (SOFA), custom high-density design
+
+filesets:
+  rtl:
+    files:
+      - FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.top_only.pt.v
+    file_type: verilogSource
+
+targets:
+  default:
+    filesets: [rtl]
+
+provider:
+  name    : github
+  user    : lnis-uofu
+  repo    : SOFA
+  version : 47b839fa0aafcef897674d4cf7c3a465f4a65e88

openfpga/sofa-hd.core

@@ -0,0 +1,20 @@
+CAPI=2:
+
+name: openfpga:cores:sofa-hd:1.0
+description: Hard-IP 12x12 FPGA core, Skywater Open-source FpgA (SOFA), high-density design
+
+filesets:
+  rtl:
+    files:
+      - FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.top_only.pt.v
+    file_type: verilogSource
+
+targets:
+  default:
+    filesets: [rtl]
+
+provider:
+  name    : github
+  user    : lnis-uofu
+  repo    : SOFA
+  version : 47b839fa0aafcef897674d4cf7c3a465f4a65e88

openfpga/sofa-qlhd.core

@@ -0,0 +1,20 @@
+CAPI=2:
+
+name: openfpga:cores:sofa-qlhd:1.0
+description: Hard-IP 12x12 FPGA core, Skywater Open-source FpgA (SOFA), QuickLogic' soft-adder and high-density design
+
+filesets:
+  rtl:
+    files:
+      - FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.top_only.pt.v
+    file_type: verilogSource
+
+targets:
+  default:
+    filesets: [rtl]
+
+provider:
+  name    : github
+  user    : lnis-uofu
+  repo    : SOFA
+  version : 47b839fa0aafcef897674d4cf7c3a465f4a65e88