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Updated techmaps for dsp48e1 #3411

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Sep 25, 2023
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Updated techmaps for dsp48e1 #3411

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eda62e0
added vivado target for the dsp test and modified techmaps to produce…
ad-astra-et-ultra Sep 20, 2023
8681627
Updated submodule: f4pga-arch-defs/third_party/f4pga-xc-fasm2bels
ad-astra-et-ultra Sep 25, 2023
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2 changes: 1 addition & 1 deletion third_party/f4pga-xc-fasm2bels
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Submodule f4pga-xc-fasm2bels updated from 24d1e3 to 631939
34 changes: 17 additions & 17 deletions xilinx/common/primitives/dsp48e1/dsp48e1.pb_type.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -378,23 +378,23 @@ BREG_0=BREG_0
BREG_2=BREG_2
B_INPUT[0]=B_INPUT
MASK[47:0]=MASK
ZADREG[0]=ADREG
ZALUMODEREG[0]=ALUMODEREG
ZAREG_2_ACASCREG_1=ACASCREG
ZBREG_2_BCASCREG_1=BCASCREG
ZCARRAYINREG[0]=CARRAYINREG
ZCARRYINSELREG[0]=CARRYINSELREG
ZDREG[0]=DREG
ZINMODEREG[0]=INMODEREG
ZMREG[0]=MREG
ZOPMODEREG[0]=OPMODEREG
ZPREG[0]=PREG
ZCREG[0]=CREG
ZIS_ALUMODE_INVERTED[3:0]=IS_ALUMODE_INVERTED
ZIS_INMODE_INVERTED[4:0]=IS_INMODE_INVERTED
ZIS_OPMODE_INVERTED[6:0]=IS_OPMODE_INVERTED
ZIS_CLK_INVERTED=IS_CLK_INVERTED
ZIS_CARRYIN_INVERTED=IS_CARRYIN_INVERTED
ZADREG[0]=ZADREG
ZALUMODEREG[0]=ZALUMODEREG
ZAREG_2_ACASCREG_1=ZAREG_2_ACASCREG_1
ZBREG_2_BCASCREG_1=ZBREG_2_BCASCREG_1
ZCARRAYINREG[0]=ZCARRAYINREG
ZCARRYINSELREG[0]=ZCARRYINSELREG
ZDREG[0]=ZDREG
ZINMODEREG[0]=ZINMODEREG
ZMREG[0]=ZMREG
ZOPMODEREG[0]=ZOPMODEREG
ZPREG[0]=ZPREG
ZCREG[0]=ZCREG
ZIS_ALUMODE_INVERTED[3:0]=ZIS_ALUMODE_INVERTED
ZIS_INMODE_INVERTED[4:0]=ZIS_INMODE_INVERTED
ZIS_OPMODE_INVERTED[6:0]=ZIS_OPMODE_INVERTED
ZIS_CLK_INVERTED=ZIS_CLK_INVERTED
ZIS_CARRYIN_INVERTED=ZIS_CARRYIN_INVERTED
USE_SIMD_FOUR12_TWO24=USE_SIMD_FOUR12_TWO24
USE_SIMD_FOUR12=USE_SIMD_FOUR12
USE_DPORT[0]=USE_DPORT
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34 changes: 17 additions & 17 deletions xilinx/xc7/techmap/cells_map.v
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Original file line number Diff line number Diff line change
Expand Up @@ -11032,21 +11032,21 @@ module DSP48E1 (
.AREG_2(AREG==2),
.BREG_2(BREG==2),
.MASK(MASK),
.ADREG(ADREG[0]),
.ALUMODEREG(ALUMODEREG[0]),
.ACASCREG(AREG==2 && ACASCREG==1),
.BCASCREG(BREG==2 && BCASCREG==1),
.CARRYINREG(CARRYINREG[0]),
.CARRYINSELREG(CARRYINSELREG[0]),
.DREG(DREG[0]),
.INMODEREG(INMODEREG[0]),
.IS_ALUMODE_INVERTED(IS_ALUMODE_INVERTED),
.IS_INMODE_INVERTED(IS_INMODE_INVERTED),
.IS_OPMODE_INVERTED(IS_OPMODE_INVERTED),
.MREG(MREG[0]),
.OPMODEREG(OPMODEREG[0]),
.PREG(PREG[0]),
.CREG(CREG[0]),
.ZADREG(~ADREG[0]),
.ZALUMODEREG(~ALUMODEREG[0]),
.ZAREG_2_ACASCREG_1(~(AREG==2 && ACASCREG==1)),
.ZBREG_2_BCASCREG_1(~(BREG==2 && BCASCREG==1)),
.ZCARRYINREG(~CARRYINREG[0]),
.ZCARRYINSELREG(~CARRYINSELREG[0]),
.ZDREG(~DREG[0]),
.ZINMODEREG(~INMODEREG[0]),
.ZIS_ALUMODE_INVERTED(~IS_ALUMODE_INVERTED),
.ZIS_INMODE_INVERTED(~IS_INMODE_INVERTED),
.ZIS_OPMODE_INVERTED(~IS_OPMODE_INVERTED),
.ZMREG(~MREG[0]),
.ZOPMODEREG(~OPMODEREG[0]),
.ZPREG(~PREG[0]),
.ZCREG(~CREG[0]),
.A_INPUT(A_INPUT == "CASCADE"),
.B_INPUT(B_INPUT == "CASCADE"),
.USE_DPORT(USE_DPORT == "TRUE"),
Expand All @@ -11058,8 +11058,8 @@ module DSP48E1 (
.SEL_MASK_ROUNDING_MODE1(SEL_MASK == "ROUNDING_MODE1"),
.SEL_MASK_ROUNDING_MODE2(SEL_MASK == "ROUNDING_MODE2"),
.SEL_MASK_C(SEL_MASK == "C"),
.IS_CARRYIN_INVERTED(IS_CARRYIN_INVERTED),
.IS_CLK_INVERTED(IS_CLK_INVERTED)
.ZIS_CARRYIN_INVERTED(~IS_CARRYIN_INVERTED),
.ZIS_CLK_INVERTED(~IS_CLK_INVERTED)

) _TECHMAP_REPLACE_ (
.ACOUT(ACOUT),
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34 changes: 17 additions & 17 deletions xilinx/xc7/techmap/cells_sim.v
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Original file line number Diff line number Diff line change
Expand Up @@ -3633,18 +3633,18 @@ module DSP48E1_VPR (
parameter BREG_2 = 1'b0;
parameter MASK = 48'b000000000000000000000000000000000000000000000000;
parameter PATTERN = 48'b000000000000000000000000000000000000000000000000;
parameter ADREG = 1'b0;
parameter ALUMODEREG = 1'b0;
parameter ACASCREG = 1'b0;
parameter BCASCREG = 1'b0;
parameter CARRYINREG = 1'b0;
parameter CARRYINSELREG = 1'b0;
parameter DREG = 1'b0;
parameter INMODEREG = 1'b0;
parameter MREG = 1'b0;
parameter OPMODEREG = 1'b0;
parameter PREG = 1'b0;
parameter CREG = 1'b0;
parameter ZADREG = 1'b1;
parameter ZALUMODEREG = 1'b1;
parameter ZAREG_2_ACASCREG_1 = 1'b1;
parameter ZBREG_2_BCASCREG_1 = 1'b1;
parameter ZCARRYINREG = 1'b1;
parameter ZCARRYINSELREG = 1'b1;
parameter ZDREG = 1'b1;
parameter ZINMODEREG = 1'b1;
parameter ZMREG = 1'b1;
parameter ZOPMODEREG = 1'b1;
parameter ZPREG = 1'b1;
parameter ZCREG = 1'b1;
parameter A_INPUT = 1'b0;
parameter B_INPUT = 1'b0;
parameter USE_DPORT = 1'b0;
Expand All @@ -3655,9 +3655,9 @@ module DSP48E1_VPR (
parameter SEL_MASK_ROUNDING_MODE1 = 1'b0;
parameter SEL_MASK_ROUNDING_MODE2 = 1'b0;
parameter SEL_MASK_C = 1'b0;
parameter [3:0] IS_ALUMODE_INVERTED = 4'b0;
parameter [4:0] IS_INMODE_INVERTED = 5'b0;
parameter [6:0] IS_OPMODE_INVERTED = 7'b0;
parameter IS_CARRYIN_INVERTED = 1'b0;
parameter IS_CLK_INVERTED = 1'b0;
parameter [3:0] ZIS_ALUMODE_INVERTED = 4'b1111;
parameter [4:0] ZIS_INMODE_INVERTED = 5'b11111;
parameter [6:0] ZIS_OPMODE_INVERTED = 7'b1111111;
parameter ZIS_CARRYIN_INVERTED = 1'b1;
parameter ZIS_CLK_INVERTED = 1'b1;
endmodule
6 changes: 6 additions & 0 deletions xilinx/xc7/tests/dsp/CMakeLists.txt
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Original file line number Diff line number Diff line change
@@ -1,9 +1,15 @@
add_file_target(FILE dsp.xdc)
add_file_target(FILE top.v SCANNER_TYPE verilog)

add_fpga_target(
NAME dsp
BOARD arty-full
SOURCES top.v
INPUT_XDC_FILES dsp.xdc
EXPLICIT_ADD_FILE_TARGET
)

add_vivado_target(
NAME dsp_vivado
PARENT_NAME dsp
)
1 change: 1 addition & 0 deletions xilinx/xc7/tests/dsp/dsp.xdc
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Expand Up @@ -58,3 +58,4 @@ set_property PACKAGE_PIN T13 [get_ports {OUT[4]}]
set_property PACKAGE_PIN A11 [get_ports {B[16]}]
set_property PACKAGE_PIN T9 [get_ports {OUT[2]}]
set_property PACKAGE_PIN J18 [get_ports {A[3]}]
set_property PACKAGE_PIN A9 [get_ports {Cin}]
53 changes: 27 additions & 26 deletions xilinx/xc7/tests/dsp/top.v
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Original file line number Diff line number Diff line change
Expand Up @@ -4,15 +4,17 @@ module top
(
A,
B,
Cin,
OUT
);


(* IOSTANDARD = "LVCMOS33" *) input wire [24:0] A;
(* IOSTANDARD = "LVCMOS33" *) input wire [17:0] B;
(* IOSTANDARD = "LVCMOS33" *) input wire Cin;
(* IOSTANDARD = "LVCMOS33" *) output wire [16:0] OUT;


DSP48E1 #(
.AREG(2'b10),
.BREG(2'b10),
Expand All @@ -25,44 +27,43 @@ module top
.CARRYINSELREG(1'b0),
.DREG(1'b0),
.INMODEREG(1'b0),
.IS_ALUMODE_INVERTED(4'b1101),
.IS_INMODE_INVERTED(5'b11111),
.IS_OPMODE_INVERTED(7'b1000101),
.IS_ALUMODE_INVERTED(4'b0000),
.IS_INMODE_INVERTED(5'b00000),
.IS_OPMODE_INVERTED(7'b00000),
.MREG(1'b0),
.OPMODEREG(1'b0),
.PREG(1'b0),
.CREG(1'b0),
.A_INPUT("CASCADE"),
.B_INPUT("CASCADE"),
.USE_DPORT("TRUE"),
.USE_SIMD("FOUR12"),
.AUTORESET_PATDET("RESET_MATCH"),
.PATTERN(48'b111110111111101111111111100001111011110111111101),
.SEL_MASK("ROUNDING_MODE1"),
.IS_CARRYIN_INVERTED(1'b1),
.IS_CLK_INVERTED(1'b1)
.IS_CARRYIN_INVERTED(1'b0),
.IS_CLK_INVERTED(1'b1)
)
dsp25x18(
.A(A),
.ALUMODE(4'b0011),
.B(B),
.C(48'b111111111111111111111111111111111111111111111111),
.CARRYIN(1'b0),
.CARRYINSEL(3'b000),
.CEA1(1'b1),
.CEA2(1'b1),
.CEAD(1'b1),
.CEALUMODE(1'b1),
.CEB1(1'b1),
.CEB2(1'b1),
.CEC(1'b1),
.CECARRYIN(1'b1),
.CECTRL(1'b1),
.CED(1'b1),
.CEINMODE(1'b1),
.CEM(1'b1),
.CEP(1'b1),
.CLK(1'b1),
.C(48'b111111111111111111111111111111111111111111111111),
.CARRYIN(Cin),
.CARRYINSEL(3'b000),
.CEA1(1'b1),
.CEA2(1'b1),
.CEAD(1'b1),
.CEALUMODE(1'b1),
.CEB1(1'b1),
.CEB2(1'b1),
.CEC(1'b1),
.CECARRYIN(1'b1),
.CECTRL(1'b1),
.CED(1'b1),
.CEINMODE(1'b1),
.CEM(1'b1),
.CEP(1'b1),
.CLK(1'b1),
.D(25'b0000000000000000000000000),
.INMODE(5'b00000),
.OPMODE(7'b0111111),
Expand Down
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