Merge branch 'refactor/avoid_float_type_in_hal' into 'master'

refactor(hal): avoid float type in hal

See merge request espressif/esp-idf!26149

components/driver/deprecated/i2s_legacy.c

@@ -1337,7 +1337,7 @@ static esp_err_t i2s_config_transfer(i2s_port_t i2s_num, const i2s_config_t *i2s
 #if SOC_I2S_HW_VERSION_2
         SLOT_CFG(pdm_tx).line_mode = I2S_PDM_TX_ONE_LINE_CODEC;
         SLOT_CFG(pdm_tx).hp_en = true;
-        SLOT_CFG(pdm_tx).hp_cut_off_freq_hz = 49;
+        SLOT_CFG(pdm_tx).hp_cut_off_freq_hzx10 = 490;
         SLOT_CFG(pdm_tx).sd_dither = 0;
         SLOT_CFG(pdm_tx).sd_dither2 = 1;
 #endif // SOC_I2S_HW_VERSION_2

components/driver/i2s/i2s_pdm.c

@@ -106,7 +106,12 @@ static esp_err_t i2s_pdm_tx_set_slot(i2s_chan_handle_t handle, const i2s_pdm_tx_
     portENTER_CRITICAL(&g_i2s.spinlock);
     /* Configure the hardware to apply PDM format */
     bool is_slave = handle->role == I2S_ROLE_SLAVE;
-    i2s_hal_pdm_set_tx_slot(&(handle->controller->hal), is_slave, (i2s_hal_slot_config_t *)slot_cfg);
+    i2s_hal_slot_config_t *slot_hal_cfg = (i2s_hal_slot_config_t *)slot_cfg;
+#if SOC_I2S_HW_VERSION_2
+    /* Times 10 to transform the float type to integer because we should avoid float type in hal */
+    slot_hal_cfg->pdm_tx.hp_cut_off_freq_hzx10 = (uint32_t)(slot_cfg->hp_cut_off_freq_hz * 10);
+#endif
+    i2s_hal_pdm_set_tx_slot(&(handle->controller->hal), is_slave, slot_hal_cfg);
     portEXIT_CRITICAL(&g_i2s.spinlock);
 
     /* Update the mode info: slot configuration */

components/esp_adc/test_apps/adc/main/CMakeLists.txt

@@ -9,5 +9,5 @@ set(srcs "test_app_main.c"
 # In order for the cases defined by `TEST_CASE` to be linked into the final elf,
 # the component can be registered as WHOLE_ARCHIVE
 idf_component_register(SRCS ${srcs}
-                       PRIV_REQUIRES driver esp_wifi nvs_flash esp_adc test_utils
+                       PRIV_REQUIRES driver esp_wifi nvs_flash esp_adc test_utils efuse
                        WHOLE_ARCHIVE)

components/esp_adc/test_apps/adc/main/test_app_main.c

@@ -7,6 +7,16 @@
 #include "unity.h"
 #include "unity_test_utils.h"
 #include "esp_heap_caps.h"
+#include "soc/soc_caps.h"
+#include "sdkconfig.h"
+#if CONFIG_IDF_TARGET_ESP32S2
+#include "esp_efuse_rtc_table.h"
+#define esp_efuse_rtc_calib_get_ver()     esp_efuse_rtc_table_read_calib_version()
+#elif SOC_ADC_CALIBRATION_V1_SUPPORTED
+#include "esp_efuse_rtc_calib.h"
+#else
+#define esp_efuse_rtc_calib_get_ver()     -1        // Not support calibration
+#endif
 
 #define TEST_MEMORY_LEAK_THRESHOLD (600)
 
@@ -33,5 +43,7 @@ void app_main(void)
     printf("  | |/ _ \\/ __| __|   / _ \\ | | | | |    \n");
     printf("  | |  __/\\__ \\ |_   / ___ \\| |_| | |___ \n");
     printf("  |_|\\___||___/\\__| /_/   \\_\\____/ \\____|\n");
+
+    printf("\nADC eFuse Calibration Version %d\n", esp_efuse_rtc_calib_get_ver());
     unity_run_menu();
 }

components/hal/esp32/clk_tree_hal.c

@@ -96,13 +96,14 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
 
 uint32_t clk_hal_apll_get_freq_hz(void)
 {
-    uint32_t xtal_freq_mhz = clk_hal_xtal_get_freq_mhz();
+    uint64_t xtal_freq_hz = clk_hal_xtal_get_freq_mhz() * MHZ ;
     uint32_t o_div = 0;
     uint32_t sdm0 = 0;
     uint32_t sdm1 = 0;
     uint32_t sdm2 = 0;
     clk_ll_apll_get_config(&o_div, &sdm0, &sdm1, &sdm2);
-    uint32_t apll_freq_hz = (uint32_t)(xtal_freq_mhz * MHZ * (4 + sdm2 + (float)sdm1/256.0 + (float)sdm0/65536.0) /
-                            (((float)o_div + 2) * 2));
+    uint32_t numerator = ((4 + sdm2) << 16) | (sdm1 << 8) | sdm0;
+    uint32_t denominator = (o_div + 2) << 17;
+    uint32_t apll_freq_hz = (uint32_t)((xtal_freq_hz * numerator) / denominator);
     return apll_freq_hz;
 }

components/hal/esp32h2/include/hal/ana_cmpr_ll.h

@@ -45,11 +45,11 @@ static inline void analog_cmpr_ll_set_internal_ref_voltage(analog_cmpr_dev_t *hw
  * @brief Get the voltage of the internal reference
  *
  * @param hw Analog comparator register base address
- * @return The voltage of the internal reference
+ * @return The voltage of the internal reference times 10
  */
-static inline float analog_cmpr_ll_get_internal_ref_voltage(analog_cmpr_dev_t *hw)
+static inline uint32_t analog_cmpr_ll_get_internal_ref_voltage(analog_cmpr_dev_t *hw)
 {
-    return hw->pad_comp_config->dref_comp * 0.1F;
+    return hw->pad_comp_config->dref_comp;
 }
 
 /**

components/hal/esp32s2/clk_tree_hal.c

@@ -100,13 +100,14 @@ uint32_t clk_hal_xtal_get_freq_mhz(void)
 
 uint32_t clk_hal_apll_get_freq_hz(void)
 {
-    uint32_t xtal_freq_mhz = clk_hal_xtal_get_freq_mhz();
+    uint64_t xtal_freq_hz = clk_hal_xtal_get_freq_mhz() * MHZ ;
     uint32_t o_div = 0;
     uint32_t sdm0 = 0;
     uint32_t sdm1 = 0;
     uint32_t sdm2 = 0;
     clk_ll_apll_get_config(&o_div, &sdm0, &sdm1, &sdm2);
-    uint32_t apll_freq_hz = (uint32_t)(xtal_freq_mhz * MHZ * (4 + sdm2 + (float)sdm1/256.0 + (float)sdm0/65536.0) /
-                            (((float)o_div + 2) * 2));
+    uint32_t numerator = ((4 + sdm2) << 16) | (sdm1 << 8) | sdm0;
+    uint32_t denominator = (o_div + 2) << 17;
+    uint32_t apll_freq_hz = (uint32_t)((xtal_freq_hz * numerator) / denominator);
     return apll_freq_hz;
 }

components/hal/i2s_hal.c

@@ -12,24 +12,25 @@
 
 #if SOC_I2S_HW_VERSION_2 && (SOC_I2S_SUPPORTS_PDM_TX || SOC_I2S_SUPPORTS_PDM_RX_HP_FILTER)
 /* PDM tx high pass filter cut-off frequency and coefficients list
- * [0]: cut-off frequency; [1]: param0; [2]: param5 */
-static const float cut_off_coef[21][3] = {
-    {185, 0, 0}, {172,  0, 1}, {160,  1, 1},
-    {150, 1, 2}, {137,  2, 2}, {126,  2, 3},
-    {120, 0, 3}, {115,  3, 3}, {106,  1, 7},
-    {104, 2, 4}, {92,   4, 4}, {91.5, 2, 7},
-    {81,  4, 5}, {77.2, 3, 7}, {69,   5, 5},
-    {63,  4, 7}, {58,   5, 6}, {49,   5, 7},
-    {46,  6, 6}, {35.5, 6, 7}, {23.3, 7, 7}
+ * [0]: cut-off frequency * 10; [1]: param0; [2]: param5
+ * NOTE: the cut-off frequency was timed 10 to use integer type */
+static const uint32_t cut_off_coef[21][3] = {
+    {1850, 0, 0}, {1720,  0, 1}, {1600,  1, 1},
+    {1500, 1, 2}, {1370,  2, 2}, {1260,  2, 3},
+    {1200, 0, 3}, {1150,  3, 3}, {1060,  1, 7},
+    {1040, 2, 4}, {920,   4, 4}, {915, 2, 7},
+    {810,  4, 5}, {772, 3, 7}, {690,   5, 5},
+    {630,  4, 7}, {580,   5, 6}, {490,   5, 7},
+    {460,  6, 6}, {355, 6, 7}, {233, 7, 7}
 };
 
-static void s_i2s_hal_get_cut_off_coef(float freq, uint32_t *param0, uint32_t *param5)
+static void s_i2s_hal_get_cut_off_coef(uint32_t freq, uint32_t *param0, uint32_t *param5)
 {
     uint8_t cnt = 0;
-    float min = 1000;
+    uint32_t min = 10000;
     /* Find the closest cut-off frequency and its coefficients */
     for (int i = 0; i < 21; i++) {
-        float tmp = cut_off_coef[i][0] < freq ? freq - cut_off_coef[i][0] : cut_off_coef[i][0] - freq;
+        uint32_t tmp = cut_off_coef[i][0] < freq ? freq - cut_off_coef[i][0] : cut_off_coef[i][0] - freq;
         if (tmp < min) {
             min = tmp;
             cnt = i;
@@ -209,7 +210,7 @@ void i2s_hal_pdm_set_tx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_ha
     i2s_ll_tx_pdm_slot_mode(hal->dev, is_mono, false, I2S_PDM_SLOT_BOTH);
     uint32_t param0;
     uint32_t param5;
-    s_i2s_hal_get_cut_off_coef(slot_cfg->pdm_tx.hp_cut_off_freq_hz, &param0, &param5);
+    s_i2s_hal_get_cut_off_coef(slot_cfg->pdm_tx.hp_cut_off_freq_hzx10, &param0, &param5);
     i2s_ll_tx_enable_pdm_hp_filter(hal->dev, slot_cfg->pdm_tx.hp_en);
     i2s_ll_tx_set_pdm_hp_filter_param0(hal->dev, param0);
     i2s_ll_tx_set_pdm_hp_filter_param5(hal->dev, param5);

components/hal/include/hal/i2s_hal.h

@@ -81,7 +81,8 @@ typedef struct {
 #if SOC_I2S_HW_VERSION_2
             i2s_pdm_tx_line_mode_t  line_mode;          /*!< PDM TX line mode, on-line codec, one-line dac, two-line dac mode can be selected */
             bool                    hp_en;              /*!< High pass filter enable */
-            float                   hp_cut_off_freq_hz; /*!< High pass filter cut-off frequency, range 23.3Hz ~ 185Hz, see cut-off frequency sheet above */
+            uint32_t                hp_cut_off_freq_hzx10; /*!< High pass filter cut-off frequency times 10, cut-off frequency range 23.3Hz ~ 185Hz, see cut-off frequency sheet above
+                                                         *   The freq is timed 10 to use integer type */
             uint32_t                sd_dither;          /*!< Sigma-delta filter dither */
             uint32_t                sd_dither2;         /*!< Sigma-delta filter dither2 */
 #endif // SOC_I2S_HW_VERSION_2