Fixes exceptions resulting from using SPI0Command #9140
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…perations such as: Write Status Register-1, Sector Eraser, etc. Moved PRECACHE_END to ensure `Wait_SPI_Idlep` and `xt_wsr_ps` are included in the iCache. Added SPIUCSSETUP to give more settling time for #CS.
and the "target opcode". They are now tightly coupled. Update flash quirks.
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Let's put this on hold. I need to look closer at the sequence of calls used when doing write enabled by other examples. Some examples poll the status register until bit WEL is set before continuing. |
SPI_write_enable for the special handling of the WEL bit. Corrected zero mask for fractional byte returns where the partial byte bits are positioned at the most significant bit position in the byte.
Still on hold? Is this related to a specific flash chip? Or does this happen at random (or not so forced random) on any hardware? |
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It looks ready. I haven't found any more issues.
This may be me overanalyzing and being over-cautious. The BootROM's |
* Resolves exceptions occuring when using SPI0Command for flash write operations such as: Write Status Register-1, Sector Eraser, etc. Moved PRECACHE_END to ensure `Wait_SPI_Idlep` and `xt_wsr_ps` are included in the iCache. Added SPIUCSSETUP to give more settling time for #CS. * There was a risk of flash reads inserted between an "enable opcode" and the "target opcode". They are now tightly coupled. Update flash quirks. * When sending instruction Write Enable 0x06, use BootROM API SPI_write_enable for the special handling of the WEL bit. Corrected zero mask for fractional byte returns where the partial byte bits are positioned at the most significant bit position in the byte.
Resolves exceptions occurring when using
experimental::SPI0Commandfor flash write operations such as: Write Status Register-1, Sector Eraser, etc.Moved PRECACHE_END to ensure
Wait_SPI_Idlepandxt_wsr_psare included in the iCache.Added SPIUCSSETUP to give more settling time for #CS.