new cv32e40x patches

core-v-mini-mcu.core

@@ -231,6 +231,12 @@ parameters:
     description: |
       Enables testbench JTAG DIPs. Admitted values: 1|0.
     default: 0
+  X_EXT:
+    datatype: int
+    paramtype: vlogparam
+    description: |
+      Enables CORE-V-XIF interface for the CV32E40X and CV32E40PX cores. Admitted values: 1|0.
+    default: 0
   USE_EXTERNAL_DEVICE_EXAMPLE:
     datatype: int
     paramtype: vlogparam
@@ -325,6 +331,7 @@ targets:
     - COREV_PULP
     - FPU
     - JTAG_DPI
+    - X_EXT
     - USE_EXTERNAL_DEVICE_EXAMPLE
     - USE_UPF
     - REMOVE_OBI_FIFO
@@ -383,6 +390,7 @@ targets:
     parameters:
     - COREV_PULP
     - FPU
+    - X_EXT
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
     tools:
@@ -402,6 +410,7 @@ targets:
     parameters:
     - COREV_PULP
     - FPU
+    - X_EXT
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
     tools:
@@ -421,6 +430,7 @@ targets:
     parameters:
     - COREV_PULP
     - FPU
+    - X_EXT
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
     tools:
@@ -436,6 +446,7 @@ targets:
     parameters:
     - PRIM_DEFAULT_IMPL=prim_pkg::your_target_technology
     - COREV_PULP
+    - X_EXT
     - FPU
     - SYNTHESIS=true
     - REMOVE_OBI_FIFO
@@ -458,6 +469,7 @@ targets:
     parameters:
       - COREV_PULP
       - FPU
+      - X_EXT
       - SYNTHESIS=true
       - VERILATOR=true
       - REMOVE_OBI_FIFO

hw/core-v-mini-mcu/cpu_subsystem.sv

@@ -175,7 +175,7 @@ module cpu_subsystem
     // instantiate the core
     cv32e40x_core #(
         .NUM_MHPMCOUNTERS(NUM_MHPMCOUNTERS),
-        .X_EXT(X_EXT),
+        .X_EXT(X_EXT[0]),
         .DBG_NUM_TRIGGERS('0)
     ) cv32e40x_core_i (
         // Clock and reset

hw/vendor/openhwgroup_cv32e40x/rtl/cv32e40x_core.sv

@@ -400,7 +400,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
   assign dbg_ack   = ctrl_fsm.dbg_ack;
 
   // Gate off the internal debug_request signal if debug support is not configured.
-  assign debug_req_gated = DEBUG ? debug_req_i : 1'b0;
+  assign debug_req_gated = (DEBUG != 0) ? debug_req_i : 1'b0;
 
   //////////////////////////////////////////////////////////////////////////////////////////////
   //   ____ _            _      __  __                                                   _    //

hw/vendor/openhwgroup_cv32e40x/rtl/cv32e40x_cs_registers.sv

@@ -271,13 +271,14 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
 
 
   // Performance Counter Signals
-  logic [31:0] [63:0]           mhpmcounter_q;                                  // Performance counters
+  logic [63:0]                  mhpmcounter_q[32];                              // Performance counters
   logic [31:0] [63:0]           mhpmcounter_n;                                  // Performance counters next value
   logic [31:0] [63:0]           mhpmcounter_rdata;                              // Performance counters next value
   logic [31:0] [1:0]            mhpmcounter_we;                                 // Performance counters write enable
   logic [31:0] [31:0]           mhpmevent_q, mhpmevent_n, mhpmevent_rdata;      // Event enable
   logic [31:0]                  mcountinhibit_q, mcountinhibit_n, mcountinhibit_rdata; // Performance counter inhibit
-  logic [NUM_HPM_EVENTS-1:0]    hpm_events;                                     // Events for performance counters
+  logic                         hpm_events[NUM_HPM_EVENTS];                     // Events for performance counters
+  logic [NUM_HPM_EVENTS-1:0]    packed_hpm_events;                              // Packed Events for performance counters
   logic [31:0] [63:0]           mhpmcounter_increment;                          // Increment of mhpmcounter_q
   logic [31:0]                  mhpmcounter_write_lower;                        // Write 32 lower bits of mhpmcounter_q
   logic [31:0]                  mhpmcounter_write_upper;                        // Write 32 upper bits mhpmcounter_q
@@ -535,7 +536,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
       end
 
       CSR_DCSR: begin
-        if (DEBUG) begin
+        if (DEBUG != 0) begin
           csr_rdata_int = dcsr_rdata;
           illegal_csr_read = !ctrl_fsm_i.debug_mode;
         end else begin
@@ -545,7 +546,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
       end
 
       CSR_DPC: begin
-        if (DEBUG) begin
+        if (DEBUG != 0) begin
           csr_rdata_int = dpc_rdata;
           illegal_csr_read = !ctrl_fsm_i.debug_mode;
         end else begin
@@ -555,7 +556,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
       end
 
       CSR_DSCRATCH0: begin
-        if (DEBUG) begin
+        if (DEBUG != 0) begin
           csr_rdata_int = dscratch0_rdata;
           illegal_csr_read = !ctrl_fsm_i.debug_mode;
         end else begin
@@ -565,7 +566,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
       end
 
       CSR_DSCRATCH1: begin
-        if (DEBUG) begin
+        if (DEBUG != 0) begin
           csr_rdata_int = dscratch1_rdata;
           illegal_csr_read = !ctrl_fsm_i.debug_mode;
         end else begin
@@ -1239,7 +1240,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
   );
 
   generate
-    if (DEBUG) begin : gen_debug_csr
+    if (DEBUG != 0) begin : gen_debug_csr
       cv32e40x_csr
       #(
         .WIDTH      (32),
@@ -1533,7 +1534,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
   assign priv_lvl_rdata     = PRIV_LVL_M;
 
   // dcsr_rdata factors in the flop outputs and the nmip bit from the controller
-  assign dcsr_rdata = DEBUG ? {dcsr_q[31:4], ctrl_fsm_i.pending_nmi, dcsr_q[2:0]} : 32'h0;
+  assign dcsr_rdata = (DEBUG != 0) ? {dcsr_q[31:4], ctrl_fsm_i.pending_nmi, dcsr_q[2:0]} : 32'h0;
 
 
   assign mcause_rdata = mcause_q;
@@ -1682,6 +1683,9 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
   genvar                hpm_idx;
   generate
     for(hpm_idx=0; hpm_idx<16; hpm_idx++) begin
+
+      assign packed_hpm_events[hpm_idx] = hpm_events[hpm_idx];
+
       if(HPM_EVENT_FLOP[hpm_idx]) begin: hpm_event_flop
 
         always_ff @(posedge clk, negedge rst_n) begin
@@ -1807,14 +1811,14 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
                                                         !mhpmcounter_write_upper[wcnt_gidx] &&
                                                         !mcountinhibit_rdata[wcnt_gidx] &&
                                                         !debug_stopcount &&
-                                                        hpm_events[1];
+                                                        packed_hpm_events[1];
       end else if( (wcnt_gidx>2) && (wcnt_gidx<(NUM_MHPMCOUNTERS+3))) begin : gen_mhpmcounter
         // add +1 if any event is enabled and active
         assign mhpmcounter_write_increment[wcnt_gidx] = !mhpmcounter_write_lower[wcnt_gidx] &&
                                                         !mhpmcounter_write_upper[wcnt_gidx] &&
                                                         !mcountinhibit_rdata[wcnt_gidx] &&
                                                         !debug_stopcount &&
-                                                        |(hpm_events & mhpmevent_rdata[wcnt_gidx][NUM_HPM_EVENTS-1:0]);
+                                                        |(packed_hpm_events & mhpmevent_rdata[wcnt_gidx][NUM_HPM_EVENTS-1:0]);
       end else begin : gen_mhpmcounter_not_implemented
         assign mhpmcounter_write_increment[wcnt_gidx] = 1'b0;
       end

hw/vendor/openhwgroup_cv32e40x/rtl/cv32e40x_debug_triggers.sv

@@ -108,13 +108,13 @@ import cv32e40x_pkg::*;
       logic [DBG_NUM_TRIGGERS-1 : 0] tdata2_we_int;
 
       // CSR instance outputs
-      logic [31:0] tdata1_q[DBG_NUM_TRIGGERS];
-      logic [31:0] tdata2_q[DBG_NUM_TRIGGERS];
+      logic [31:0] tdata1_q[DBG_NUM_TRIGGERS-1:0];
+      logic [31:0] tdata2_q[DBG_NUM_TRIGGERS-1:0];
       logic [31:0] tselect_q;
 
       // CSR read data, possibly WARL resolved
-      logic [31:0] tdata1_rdata[DBG_NUM_TRIGGERS];
-      logic [31:0] tdata2_rdata[DBG_NUM_TRIGGERS];
+      logic [31:0] tdata1_rdata[DBG_NUM_TRIGGERS-1:0];
+      logic [31:0] tdata2_rdata[DBG_NUM_TRIGGERS-1:0];
 
       // IF, EX and WB stages trigger match
       logic [DBG_NUM_TRIGGERS-1 : 0] trigger_match_if;
@@ -127,7 +127,7 @@ import cv32e40x_pkg::*;
       // LSU address match signals
       logic [DBG_NUM_TRIGGERS-1 : 0] lsu_addr_match_en;
       logic [DBG_NUM_TRIGGERS-1 : 0] lsu_addr_match;
-      logic [3:0]                    lsu_byte_addr_match[DBG_NUM_TRIGGERS];
+      logic [3:0]                    lsu_byte_addr_match[DBG_NUM_TRIGGERS-1:0];
 
       // Enable matching based on privilege level per trigger
       logic [DBG_NUM_TRIGGERS-1 : 0] priv_lvl_match_en_if;
@@ -140,7 +140,7 @@ import cv32e40x_pkg::*;
       logic [31:0] lsu_addr_high;     // The highest accessed address of an LSU transaction
 
       // Exception trigger code match
-      logic [31:0] exception_match[DBG_NUM_TRIGGERS];
+      logic [31:0] exception_match[DBG_NUM_TRIGGERS-1:0];
 
       // Write data
       always_comb begin

hw/vendor/openhwgroup_cv32e40x/rtl/cv32e40x_id_stage.sv

@@ -749,7 +749,9 @@ module cv32e40x_id_stage import cv32e40x_pkg::*;
       // Also attempt to offload any CSR instruction. The validity of such instructions are only
       // checked in the EX stage.
       // Instructions with deassert_we set to 1 from the controller bypass logic will not be attempted offloaded.
-      assign xif_issue_if.issue_valid     = instr_valid && (illegal_insn || csr_en) &&
+      // Only offload instructions if the EX stage is ready not to miss data from xif_issue.issue_resp
+      assign xif_issue_if.issue_valid     = instr_valid && ex_ready_i &&
+                                            (illegal_insn || csr_en) &&
                                             !(xif_accepted_q || xif_rejected_q || ctrl_byp_i.deassert_we);
 
       // Keep xif_offloading_o high after an offloaded instruction was accepted or rejected to get

hw/vendor/openhwgroup_cv32e40x/rtl/cv32e40x_pma.sv

@@ -98,7 +98,7 @@ module cv32e40x_pma import cv32e40x_pkg::*;
 
   // Tie of atomic attribute if A_EXT=0
   generate
-    if (A_EXT) begin: pma_atomic
+    if (A_EXT != A_NONE) begin: pma_atomic
       assign pma_cfg_atomic = pma_cfg.atomic;
     end
     else begin: pma_no_atomic

hw/vendor/patches/openhwgroup_cv32e40x/cv32e40x_core.sv.patch

@@ -0,0 +1,13 @@
+diff --git a/rtl/cv32e40x_core.sv b/rtl/cv32e40x_core.sv
+index faceb96..eddd0ea 100644
+--- a/rtl/cv32e40x_core.sv
++++ b/rtl/cv32e40x_core.sv
+@@ -398,7 +398,7 @@ module cv32e40x_core import cv32e40x_pkg::*;
+   assign dbg_ack   = ctrl_fsm.dbg_ack;
+
+   // Gate off the internal debug_request signal if debug support is not configured.
+-  assign debug_req_gated = DEBUG ? debug_req_i : 1'b0;
++  assign debug_req_gated = (DEBUG != 0) ? debug_req_i : 1'b0;
+
+   //////////////////////////////////////////////////////////////////////////////////////////////
+   //   ____ _            _      __  __                                                   _    //

hw/vendor/patches/openhwgroup_cv32e40x/cv32e40x_cs_registers.sv.patch

@@ -0,0 +1,102 @@
+diff --git a/rtl/cv32e40x_cs_registers.sv b/rtl/cv32e40x_cs_registers.sv
+index 6fe90077..57908723 100644
+--- a/rtl/cv32e40x_cs_registers.sv
++++ b/rtl/cv32e40x_cs_registers.sv
+@@ -271,13 +271,14 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
+
+
+   // Performance Counter Signals
+-  logic [31:0] [63:0]           mhpmcounter_q;                                  // Performance counters
++  logic [63:0]                  mhpmcounter_q[32];                              // Performance counters
+   logic [31:0] [63:0]           mhpmcounter_n;                                  // Performance counters next value
+   logic [31:0] [63:0]           mhpmcounter_rdata;                              // Performance counters next value
+   logic [31:0] [1:0]            mhpmcounter_we;                                 // Performance counters write enable
+   logic [31:0] [31:0]           mhpmevent_q, mhpmevent_n, mhpmevent_rdata;      // Event enable
+   logic [31:0]                  mcountinhibit_q, mcountinhibit_n, mcountinhibit_rdata; // Performance counter inhibit
+-  logic [NUM_HPM_EVENTS-1:0]    hpm_events;                                     // Events for performance counters
++  logic                         hpm_events[NUM_HPM_EVENTS];                     // Events for performance counters
++  logic [NUM_HPM_EVENTS-1:0]    packed_hpm_events;                              // Packed Events for performance counters
+   logic [31:0] [63:0]           mhpmcounter_increment;                          // Increment of mhpmcounter_q
+   logic [31:0]                  mhpmcounter_write_lower;                        // Write 32 lower bits of mhpmcounter_q
+   logic [31:0]                  mhpmcounter_write_upper;                        // Write 32 upper bits mhpmcounter_q
+@@ -535,7 +536,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
+       end
+
+       CSR_DCSR: begin
+-        if (DEBUG) begin
++        if (DEBUG != 0) begin
+           csr_rdata_int = dcsr_rdata;
+           illegal_csr_read = !ctrl_fsm_i.debug_mode;
+         end else begin
+@@ -545,7 +546,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
+       end
+
+       CSR_DPC: begin
+-        if (DEBUG) begin
++        if (DEBUG != 0) begin
+           csr_rdata_int = dpc_rdata;
+           illegal_csr_read = !ctrl_fsm_i.debug_mode;
+         end else begin
+@@ -555,7 +556,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
+       end
+
+       CSR_DSCRATCH0: begin
+-        if (DEBUG) begin
++        if (DEBUG != 0) begin
+           csr_rdata_int = dscratch0_rdata;
+           illegal_csr_read = !ctrl_fsm_i.debug_mode;
+         end else begin
+@@ -565,7 +566,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
+       end
+
+       CSR_DSCRATCH1: begin
+-        if (DEBUG) begin
++        if (DEBUG != 0) begin
+           csr_rdata_int = dscratch1_rdata;
+           illegal_csr_read = !ctrl_fsm_i.debug_mode;
+         end else begin
+@@ -1239,7 +1240,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
+   );
+
+   generate
+-    if (DEBUG) begin : gen_debug_csr
++    if (DEBUG != 0) begin : gen_debug_csr
+       cv32e40x_csr
+       #(
+         .WIDTH      (32),
+@@ -1533,7 +1534,7 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
+   assign priv_lvl_rdata     = PRIV_LVL_M;
+
+   // dcsr_rdata factors in the flop outputs and the nmip bit from the controller
+-  assign dcsr_rdata = DEBUG ? {dcsr_q[31:4], ctrl_fsm_i.pending_nmi, dcsr_q[2:0]} : 32'h0;
++  assign dcsr_rdata = (DEBUG != 0) ? {dcsr_q[31:4], ctrl_fsm_i.pending_nmi, dcsr_q[2:0]} : 32'h0;
+
+
+   assign mcause_rdata = mcause_q;
+@@ -1682,6 +1683,9 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
+   genvar                hpm_idx;
+   generate
+     for(hpm_idx=0; hpm_idx<16; hpm_idx++) begin
++
++      assign packed_hpm_events[hpm_idx] = hpm_events[hpm_idx];
++
+       if(HPM_EVENT_FLOP[hpm_idx]) begin: hpm_event_flop
+
+         always_ff @(posedge clk, negedge rst_n) begin
+@@ -1807,14 +1811,14 @@ module cv32e40x_cs_registers import cv32e40x_pkg::*;
+                                                         !mhpmcounter_write_upper[wcnt_gidx] &&
+                                                         !mcountinhibit_rdata[wcnt_gidx] &&
+                                                         !debug_stopcount &&
+-                                                        hpm_events[1];
++                                                        packed_hpm_events[1];
+       end else if( (wcnt_gidx>2) && (wcnt_gidx<(NUM_MHPMCOUNTERS+3))) begin : gen_mhpmcounter
+         // add +1 if any event is enabled and active
+         assign mhpmcounter_write_increment[wcnt_gidx] = !mhpmcounter_write_lower[wcnt_gidx] &&
+                                                         !mhpmcounter_write_upper[wcnt_gidx] &&
+                                                         !mcountinhibit_rdata[wcnt_gidx] &&
+                                                         !debug_stopcount &&
+-                                                        |(hpm_events & mhpmevent_rdata[wcnt_gidx][NUM_HPM_EVENTS-1:0]);
++                                                        |(packed_hpm_events & mhpmevent_rdata[wcnt_gidx][NUM_HPM_EVENTS-1:0]);
+       end else begin : gen_mhpmcounter_not_implemented
+         assign mhpmcounter_write_increment[wcnt_gidx] = 1'b0;
+       end

hw/vendor/patches/openhwgroup_cv32e40x/cv32e40x_debug_triggers.sv.patch

@@ -0,0 +1,40 @@
+diff --git a/rtl/cv32e40x_debug_triggers.sv b/rtl/cv32e40x_debug_triggers.sv
+index 25a084d..3bd8a32 100644
+--- a/rtl/cv32e40x_debug_triggers.sv
++++ b/rtl/cv32e40x_debug_triggers.sv
+@@ -108,13 +108,13 @@ import cv32e40x_pkg::*;
+       logic [DBG_NUM_TRIGGERS-1 : 0] tdata2_we_int;
+
+       // CSR instance outputs
+-      logic [31:0] tdata1_q[DBG_NUM_TRIGGERS];
+-      logic [31:0] tdata2_q[DBG_NUM_TRIGGERS];
++      logic [31:0] tdata1_q[DBG_NUM_TRIGGERS-1:0];
++      logic [31:0] tdata2_q[DBG_NUM_TRIGGERS-1:0];
+       logic [31:0] tselect_q;
+
+       // CSR read data, possibly WARL resolved
+-      logic [31:0] tdata1_rdata[DBG_NUM_TRIGGERS];
+-      logic [31:0] tdata2_rdata[DBG_NUM_TRIGGERS];
++      logic [31:0] tdata1_rdata[DBG_NUM_TRIGGERS-1:0];
++      logic [31:0] tdata2_rdata[DBG_NUM_TRIGGERS-1:0];
+
+       // IF, EX and WB stages trigger match
+       logic [DBG_NUM_TRIGGERS-1 : 0] trigger_match_if;
+@@ -127,7 +127,7 @@ import cv32e40x_pkg::*;
+       // LSU address match signals
+       logic [DBG_NUM_TRIGGERS-1 : 0] lsu_addr_match_en;
+       logic [DBG_NUM_TRIGGERS-1 : 0] lsu_addr_match;
+-      logic [3:0]                    lsu_byte_addr_match[DBG_NUM_TRIGGERS];
++      logic [3:0]                    lsu_byte_addr_match[DBG_NUM_TRIGGERS-1:0];
+
+       // Enable matching based on privilege level per trigger
+       logic [DBG_NUM_TRIGGERS-1 : 0] priv_lvl_match_en_if;
+@@ -140,7 +140,7 @@ import cv32e40x_pkg::*;
+       logic [31:0] lsu_addr_high;     // The highest accessed address of an LSU transaction
+
+       // Exception trigger code match
+-      logic [31:0] exception_match[DBG_NUM_TRIGGERS];
++      logic [31:0] exception_match[DBG_NUM_TRIGGERS-1:0];
+
+       // Write data
+       always_comb begin