fix: brightness of pixels

thanks kevtris
ericlewis · Sep 9, 2022 · 922ab52 · 922ab52
1 parent 1a553c9
commit 922ab52
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Showing 7 changed files with 6 additions and 11 deletions.
diff --git a/dist/Cores/ericlewis.SpaceRace/bitstream.rbf_r b/dist/Cores/ericlewis.SpaceRace/bitstream.rbf_r
diff --git a/src/fpga/ap_core.qsf b/src/fpga/ap_core.qsf
@@ -760,5 +760,5 @@ set_global_assignment -name QIP_FILE core/mf_pllbase.qip
 set_global_assignment -name SIP_FILE core/mf_pllbase.sip
 set_global_assignment -name QIP_FILE core/rtl/ic.qip
 set_global_assignment -name QIP_FILE core/rtl/sound_delta.qip
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
+set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/src/fpga/apf/build_id.mif b/src/fpga/apf/build_id.mif
@@ -10,7 +10,7 @@ CONTENT
 BEGIN
 
    0E0 : 20220909;
-   0E1 : 00125750;
-   0E2 : 03eb96c2;
+   0E1 : 00144039;
+   0E2 : 344fee42;
 
 END;
diff --git a/src/fpga/core/core_top.sv b/src/fpga/core/core_top.sv
@@ -468,10 +468,7 @@ mf_pllbase mp1 (
   wire VIDEO, SCORE;
   wire HSYNC, VSYNC, HBLANK, VBLANK;
 
-  // FIXME: These video settings are not correct, they approximate at best what the original core did.
-  // trying to use any d value above 100 causes sync issues, and trying to use hex values also causes sync issues.
-  // Super duper awesome, help wanted.
-  wire [7:0]  video = VIDEO ? 8'd100 : SCORE ? 8'd100 : 8'd0;
+  wire [7:0]  video = (VIDEO ? 8'd255 : (SCORE ? 8'd187 : 8'd0));
 
   // Does not do anything - just to satisfy the top.
   wire CLK_CORE_VIDEO;
@@ -502,9 +499,7 @@ mf_pllbase mp1 (
 
     if (~(VBLANK || HBLANK)) begin
       video_de_reg <= 1;
-      video_rgb_reg[23:16] <= video;
-      video_rgb_reg[15:8]  <= video;
-      video_rgb_reg[7:0]   <= video;
+      video_rgb_reg <= {3{video}};
     end
 
     // Set HSync and VSync to be high for a single cycle on the falling edge of the HSync and VSync coming out of Space Race

diff --git a/src/fpga/output_files/ap_core.rbf b/src/fpga/output_files/ap_core.rbf
diff --git a/src/fpga/output_files/ap_core.sof b/src/fpga/output_files/ap_core.sof
diff --git a/src/fpga/output_files/bitstream.rbf_r b/src/fpga/output_files/bitstream.rbf_r