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Releases: emsec/hal

v3.1.3

12 Nov 16:14
3ed3d48
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  • GUI code refactoring
  • fix crash which occurs sometimes when invoking context menu from gate

v3.1.2

09 Nov 19:10
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  • updated existing Python decorators and added new ones for the GUI API
  • fix get_subgraph_function crashing when output_net is a nullptr

v3.1.1

05 Nov 15:22
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  • fix bug that preventes module widget from showing the full tree in some instances
  • fix missing cleaup of groupings when deleting gates, nets, or modules
  • display Python Editor Widget by default, but hide its navigation bar
  • do not display Log Widget by default anymore

v3.1.0

05 Nov 14:56
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  • new (deterministic) layouter
    • tries to minimize wire length by placing connected gates closer to each other
    • combines multiple in-/outputs into one port if driven by the same net
    • cleaner overall appearance of the graph
  • added Python tool to convert SkyWater gate libraries into a Liberty file that can be read by HAL
  • fix bug with selection within grouping widget
  • fix return code of GUI
  • fixed problems when dragging around the docking bars of widgets
  • fix detect Library Path

v3.0.2

05 Nov 14:55
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  • Focal Test Release 2

v3.0.1

05 Nov 14:55
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  • Focal Test Release

v3.0.0

29 Oct 11:37
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Added

  • new selections details widget
    • hierarchical view of all items within the current selection
      • a single item can be selected within that view
      • selected item will be highlighted in a different color than the rest of the graph view selection
      • current selection can be moved to a module or grouping by using the respective buttons
    • details section
      • shows additional details for the item selected in the hierarchical view
      • sections can be collapsed and expanded
      • right-click context menu allows to copy strings or Python code to the clipboard and change module name, type, and port names
      • added number of gates, nets, and submodules to module details widget
  • new view manager widget
    • now presented in a table view additionally containing information about the time of creation of the view
    • views can be sorted by name and date
  • gate library improvements
    • support for gate types with multi-bit pins
    • clear identification of clock pins
  • new netlist features
    • module types and named module ports (parsed from netlist or set by user)
    • support for multi-driven nets (i.e., nets with more than one source)
  • groupings
    • an interactive container for gates, nets, and modules
    • new groupings widget within the GUI to control groupings
      • allows to be filtered and sorted
      • groupings can be added to the current selection
    • members of a grouping are shown in a dedicated color within the graph view
  • new graph view features
    • Python GUI API to control the graph view
    • zoom level of graph view can now be controlled by shortcuts
  • netlist utilities
    • added function to deep copy a netlist
    • added function to get the Boolean function of a subgraph
  • state-of-the-art suite of benchmark netlists
  • new simulator plugin
    • simulates (parts of) a netlist cycle accurate
    • can export to VCD
  • added clear_caches to Netlist
  • added get_fan_in_endpoint, get_fan_out_endpoint, get_fan_in_endpoints and get_fan_out_endpoints to class Gate

CHANGED

  • double-clicking module in module widget will open it in new view
  • gate library manager now operates on file paths instead of library names
  • liberty gate library parser now supports inout ports, clock statements and bus groups
  • netlist parsers
    • VHDL and Verilog parser now use common intermediate structure for parsing
    • attribute parsing for Verilog parser
    • support for inout ports
  • all parsers and writers have been moved into plugins
  • code refactoring
    • "hal" namespace
    • TitleCase for classes
    • moved to std::filesystem internally
    • split Python API into multiple files
  • massively expanded testing coverage
  • the project is now affiliated with the Max Planck Institute for Security and Privacy
  • reworked core ownership model
    • no more shared_ptr
    • clear ownership management via unique_ptr at necessary locations
    • instances passed via non-owning raw pointers
  • updated/fixed the graph algorithms plugin by switching entirely to igraph
  • Endpoints are now managed classes as well, owned by the respective nets and passed via pointers
  • cleaned up the documentation in many parts of the core
  • inverting a Boolean function is now done using ~ instead of !

FIXED

  • cone-view now works correctly for modules
  • module widget selection is now more consistent with graph view
  • inconsistencies with case insensitivity of the VHDL parser fixed
  • delete option no longer shown for top module in right-click context menu
  • some minor memory leaks in plugin management

REMOVED

  • list of nets and gates no longer present in module details widget

DEPRECATED

  • accessing the single source of a net is superseeded by accessing its source list to support multi-driven nets
  • using !to invert a Boolean function

v2.0.0_doi

25 Feb 12:37
495ec02
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DOI Release
Note: This is an API breaking release.

Heavily improved VHDL and Verilog parsers
Updated CMake build system to use target-based configurations
Changes to gate library system
Replaced BDDs with Boolean functions
Major changes to internal representation of gate types
Allows for differentiation between LUTs, flip-flops, latches and combinational gate types
Flip-flops and latches may now specify special sequential inputs such as enable, clock, set, and reset
Replaced JSON gate libraries with liberty files
Simplified plugin system
Included igraph library
Major GUI revision
Added isolation view/cone view feature
New layouting system
Added support for hierarchization/modularization
Tons of bug fixes and smaller issues ...

v2.0.0

20 Dec 13:15
495ec02
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Note: This is an API breaking release.

  • Heavily improved VHDL and Verilog parsers
  • Updated CMake build system to use target-based configurations
  • Changes to gate library system
    • Replaced BDDs with Boolean functions
    • Major changes to internal representation of gate types
    • Allows for differentiation between LUTs, flip-flops, latches and combinational gate types
    • Flip-flops and latches may now specify special sequential inputs such as enable, clock, set, and reset
    • Replaced JSON gate libraries with liberty files
  • Simplified plugin system
  • Included igraph library
  • Major GUI revision
    • Added isolation view/cone view feature
    • New layouting system
    • Added support for hierarchization/modularization
  • Tons of bug fixes and smaller issues ...

v1.1.8

19 Sep 12:25
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  • Fix command line parsing
  • Fix parse all_options from main
  • Fixed set log option as command line parameter without stopping execution
  • Fixed assign parsing for yosys verilog output