v2.0.0_doi

DOI Release
Note: This is an API breaking release.

Heavily improved VHDL and Verilog parsers
Updated CMake build system to use target-based configurations
Changes to gate library system
Replaced BDDs with Boolean functions
Major changes to internal representation of gate types
Allows for differentiation between LUTs, flip-flops, latches and combinational gate types
Flip-flops and latches may now specify special sequential inputs such as enable, clock, set, and reset
Replaced JSON gate libraries with liberty files
Simplified plugin system
Included igraph library
Major GUI revision
Added isolation view/cone view feature
New layouting system
Added support for hierarchization/modularization
Tons of bug fixes and smaller issues ...