Update Makefile

efabless · Aug 8, 2023 · e710d12 · e710d12
1 parent c020fde
commit e710d12
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/verilog/dv/mprj_por/Makefile b/verilog/dv/mprj_por/Makefile
@@ -49,7 +49,7 @@ hex:  ${PATTERN:=.hex}
 %.vvp: %_tb.v %.hex
 ifeq ($(SIM),RTL)
 	iverilog $(SIM_DEFINES) -I $(PDK_PATH) \
-	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
+	-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(MCW_ROOT)/verilog/rtl \
 	-I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
 	$< -o $@ 
 else