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pulley: implement vector shuffle (bytecodealliance#9910)
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* impl shuffle

* raise inst size limit
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eagr authored Dec 30, 2024
1 parent 6a95189 commit 8d1c6c3
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Showing 5 changed files with 26 additions and 5 deletions.
7 changes: 5 additions & 2 deletions cranelift/codegen/src/isa/pulley_shared/inst/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -507,8 +507,11 @@ where
}

fn worst_case_size() -> CodeOffset {
// `Vconst128 { dst, imm }` is 20 bytes (3 byte opcode + dst + 16-byte imm)
20
// `VShuffle { dst, src1, src2, imm }` is 22 bytes:
// 3-byte opcode
// dst, src1, src2
// 16-byte immediate
22
}

fn ref_type_regclass(_settings: &settings::Flags) -> RegClass {
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4 changes: 4 additions & 0 deletions cranelift/codegen/src/isa/pulley_shared/lower.isle
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Expand Up @@ -1396,6 +1396,10 @@
(rule (lower (scalar_to_vector a @ (value_type $F64)))
(pulley_vinsertf64 (pulley_vconst128 0) a 0))

;;;; Rules for `shuffle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

(rule (lower (has_type $I8X16 (shuffle a b (u128_from_immediate mask))))
(pulley_vshuffle a b mask))

;;;; Rules for `swizzle` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

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3 changes: 0 additions & 3 deletions crates/wast-util/src/lib.rs
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Expand Up @@ -404,11 +404,9 @@ impl WastTest {
"misc_testsuite/simd/canonicalize-nan.wast",
"misc_testsuite/simd/issue_3327_bnot_lowering.wast",
"misc_testsuite/simd/v128-select.wast",
"spec_testsuite/proposals/annotations/simd_lane.wast",
"spec_testsuite/proposals/relaxed-simd/i32x4_relaxed_trunc.wast",
"spec_testsuite/proposals/relaxed-simd/relaxed_dot_product.wast",
"spec_testsuite/proposals/relaxed-simd/relaxed_madd_nmadd.wast",
"spec_testsuite/proposals/memory64/simd_lane.wast",
"spec_testsuite/proposals/memory64/relaxed_madd_nmadd.wast",
"spec_testsuite/proposals/memory64/relaxed_dot_product.wast",
"spec_testsuite/proposals/memory64/i32x4_relaxed_trunc.wast",
Expand All @@ -423,7 +421,6 @@ impl WastTest {
"spec_testsuite/simd_i32x4_extadd_pairwise_i16x8.wast",
"spec_testsuite/simd_i32x4_trunc_sat_f32x4.wast",
"spec_testsuite/simd_i32x4_trunc_sat_f64x2.wast",
"spec_testsuite/simd_lane.wast",
"spec_testsuite/simd_load.wast",
"spec_testsuite/simd_splat.wast",
];
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14 changes: 14 additions & 0 deletions pulley/src/interp.rs
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Expand Up @@ -4538,6 +4538,20 @@ impl ExtendedOpVisitor for Interpreter<'_> {
ControlFlow::Continue(())
}

fn vshuffle(&mut self, dst: VReg, src1: VReg, src2: VReg, mask: u128) -> ControlFlow<Done> {
let a = self.state[src1].get_u8x16();
let b = self.state[src2].get_u8x16();
let result = mask.to_le_bytes().map(|m| {
if m < 16 {
a[m as usize]
} else {
b[m as usize - 16]
}
});
self.state[dst].set_u8x16(result);
ControlFlow::Continue(())
}

fn vswizzlei8x16(&mut self, operands: BinaryOperands<VReg>) -> ControlFlow<Done> {
let src1 = self.state[operands.src1].get_i8x16();
let src2 = self.state[operands.src2].get_i8x16();
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3 changes: 3 additions & 0 deletions pulley/src/lib.rs
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Expand Up @@ -1227,6 +1227,9 @@ macro_rules! for_each_extended_op {
/// `dst = ieee_minimum(src1, src2)`
vminimumf64x2 = Vminimumf64x2 { operands: BinaryOperands<VReg> };

/// `dst = shuffle(src1, src2, mask)`
vshuffle = VShuffle { dst: VReg, src1: VReg, src2: VReg, mask: u128 };

/// `dst = swizzle(src1, src2)`
vswizzlei8x16 = Vswizzlei8x16 { operands: BinaryOperands<VReg> };

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