Linux Kernel 3.10.12 compiles and runs (.rej cleaned up)

Applied:
/LineageOS/android/kernel/sony/msm8994$ patch -p1 -R <
/home/dj/Downloads/linuxkernelpatches/patch-3.10.12-13

Leaving out revert:

1) arch/arm64/kernel/perf_event.c - due to discrepancy

Change-Id: I89e8c7c099c45b50b9cc6958c01d79db5f245e6a
--- arch/arm64/kernel/perf_event.c
+++ arch/arm64/kernel/perf_event.c
@@ -781,7 +778,7 @@ static const unsigned
armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 /*
  * PMXEVTYPER: Event selection reg
  */
-#define	ARMV8_EVTYPE_MASK	0xc80000ff	/* Mask for
writable bits */
+#define	ARMV8_EVTYPE_MASK	0xc00000ff	/* Mask for
writable bits */

/*
 * PMXEVTYPER: Event selection reg
 */
writable bits */

2) drivers/mtd/ubi/wl.c - just memory freeing, therefore leaving out
3) drivers/usb/dwc3/gadget.c - due to discrepancy
4) drivers/usb/host/xhci.c - all reverts encapsulated with #ifndef
CONFIG_USB_DEFAULT_PERSIST
5) driver/usb/host/xhci.h - #define removal not necessary
6) fs/fuse/fuse_i.h - commented out instead of removing

Documentation/DocBook/media_api.tmpl

@@ -1,6 +1,6 @@
 <?xml version="1.0"?>
-<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.2//EN"
-	"http://www.oasis-open.org/docbook/xml/4.2/docbookx.dtd" [
+<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
+	"http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" [
 <!ENTITY % media-entities SYSTEM "./media-entities.tmpl"> %media-entities;
 <!ENTITY media-indices SYSTEM "./media-indices.tmpl">
 

Makefile

@@ -1,6 +1,6 @@
 VERSION = 3
 PATCHLEVEL = 10
-SUBLEVEL = 13
+SUBLEVEL = 12
 EXTRAVERSION =
 NAME = TOSSUG Baby Fish
 

arch/arm/boot/dts/at91rm9200.dtsi

@@ -35,12 +35,8 @@
 		ssc2 = &ssc2;
 	};
 	cpus {
-		#address-cells = <0>;
-		#size-cells = <0>;
-
-		cpu {
+		cpu@0 {
 			compatible = "arm,arm920t";
-			device_type = "cpu";
 		};
 	};
 

arch/arm/boot/dts/at91sam9260.dtsi

@@ -32,12 +32,8 @@
 		ssc0 = &ssc0;
 	};
 	cpus {
-		#address-cells = <0>;
-		#size-cells = <0>;
-
-		cpu {
-			compatible = "arm,arm926ej-s";
-			device_type = "cpu";
+		cpu@0 {
+			compatible = "arm,arm926ejs";
 		};
 	};
 

arch/arm/boot/dts/at91sam9263.dtsi

@@ -29,12 +29,8 @@
 		ssc1 = &ssc1;
 	};
 	cpus {
-		#address-cells = <0>;
-		#size-cells = <0>;
-
-		cpu {
-			compatible = "arm,arm926ej-s";
-			device_type = "cpu";
+		cpu@0 {
+			compatible = "arm,arm926ejs";
 		};
 	};
 

arch/arm/boot/dts/at91sam9g45.dtsi

@@ -35,12 +35,8 @@
 		ssc1 = &ssc1;
 	};
 	cpus {
-		#address-cells = <0>;
-		#size-cells = <0>;
-
-		cpu {
-			compatible = "arm,arm926ej-s";
-			device_type = "cpu";
+		cpu@0 {
+			compatible = "arm,arm926ejs";
 		};
 	};
 

arch/arm/boot/dts/at91sam9n12.dtsi

@@ -31,12 +31,8 @@
 		ssc0 = &ssc0;
 	};
 	cpus {
-		#address-cells = <0>;
-		#size-cells = <0>;
-
-		cpu {
-			compatible = "arm,arm926ej-s";
-			device_type = "cpu";
+		cpu@0 {
+			compatible = "arm,arm926ejs";
 		};
 	};
 

arch/arm/boot/dts/at91sam9x5.dtsi

@@ -33,12 +33,8 @@
 		ssc0 = &ssc0;
 	};
 	cpus {
-		#address-cells = <0>;
-		#size-cells = <0>;
-
-		cpu {
-			compatible = "arm,arm926ej-s";
-			device_type = "cpu";
+		cpu@0 {
+			compatible = "arm,arm926ejs";
 		};
 	};
 

arch/arm/boot/dts/sama5d3.dtsi

@@ -35,12 +35,8 @@
 		ssc1 = &ssc1;
 	};
 	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
 		cpu@0 {
-			device_type = "cpu";
 			compatible = "arm,cortex-a5";
-			reg = <0x0>;
 		};
 	};
 

arch/arm/boot/dts/sun4i-a10.dtsi

@@ -16,12 +16,8 @@
 	interrupt-parent = <&intc>;
 
 	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
 		cpu@0 {
-			device_type = "cpu";
 			compatible = "arm,cortex-a8";
-			reg = <0x0>;
 		};
 	};
 

arch/arm/boot/dts/sun5i-a13.dtsi

@@ -17,12 +17,8 @@
 	interrupt-parent = <&intc>;
 
 	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
 		cpu@0 {
-			device_type = "cpu";
 			compatible = "arm,cortex-a8";
-			reg = <0x0>;
 		};
 	};
 

arch/arm/kvm/coproc.c

@@ -146,20 +146,16 @@ static bool pm_fake(struct kvm_vcpu *vcpu,
 #define access_pmintenclr pm_fake
 
 /* Architected CP15 registers.
- * CRn denotes the primary register number, but is copied to the CRm in the
- * user space API for 64-bit register access in line with the terminology used
- * in the ARM ARM.
- * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
- *            registers preceding 32-bit ones.
+ * Important: Must be sorted ascending by CRn, CRM, Op1, Op2
  */
 static const struct coproc_reg cp15_regs[] = {
 	/* CSSELR: swapped by interrupt.S. */
 	{ CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
 			NULL, reset_unknown, c0_CSSELR },
 
 	/* TTBR0/TTBR1: swapped by interrupt.S. */
-	{ CRm64( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
-	{ CRm64( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
+	{ CRm( 2), Op1( 0), is64, NULL, reset_unknown64, c2_TTBR0 },
+	{ CRm( 2), Op1( 1), is64, NULL, reset_unknown64, c2_TTBR1 },
 
 	/* TTBCR: swapped by interrupt.S. */
 	{ CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
@@ -186,7 +182,7 @@ static const struct coproc_reg cp15_regs[] = {
 			NULL, reset_unknown, c6_IFAR },
 
 	/* PAR swapped by interrupt.S */
-	{ CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
+	{ CRn( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
 
 	/*
 	 * DC{C,I,CI}SW operations:
@@ -403,13 +399,12 @@ static bool index_to_params(u64 id, struct coproc_params *params)
 			      | KVM_REG_ARM_OPC1_MASK))
 			return false;
 		params->is_64bit = true;
-		/* CRm to CRn: see cp15_to_index for details */
-		params->CRn = ((id & KVM_REG_ARM_CRM_MASK)
+		params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
 			       >> KVM_REG_ARM_CRM_SHIFT);
 		params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
 			       >> KVM_REG_ARM_OPC1_SHIFT);
 		params->Op2 = 0;
-		params->CRm = 0;
+		params->CRn = 0;
 		return true;
 	default:
 		return false;
@@ -903,14 +898,7 @@ static u64 cp15_to_index(const struct coproc_reg *reg)
 	if (reg->is_64) {
 		val |= KVM_REG_SIZE_U64;
 		val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
-		/*
-		 * CRn always denotes the primary coproc. reg. nr. for the
-		 * in-kernel representation, but the user space API uses the
-		 * CRm for the encoding, because it is modelled after the
-		 * MRRC/MCRR instructions: see the ARM ARM rev. c page
-		 * B3-1445
-		 */
-		val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT);
+		val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
 	} else {
 		val |= KVM_REG_SIZE_U32;
 		val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);

arch/arm/kvm/coproc.h

@@ -135,8 +135,6 @@ static inline int cmp_reg(const struct coproc_reg *i1,
 		return -1;
 	if (i1->CRn != i2->CRn)
 		return i1->CRn - i2->CRn;
-	if (i1->is_64 != i2->is_64)
-		return i2->is_64 - i1->is_64;
 	if (i1->CRm != i2->CRm)
 		return i1->CRm - i2->CRm;
 	if (i1->Op1 != i2->Op1)
@@ -147,7 +145,6 @@ static inline int cmp_reg(const struct coproc_reg *i1,
 
 #define CRn(_x)		.CRn = _x
 #define CRm(_x) 	.CRm = _x
-#define CRm64(_x)       .CRn = _x, .CRm = 0
 #define Op1(_x) 	.Op1 = _x
 #define Op2(_x) 	.Op2 = _x
 #define is64		.is_64 = true

arch/arm/kvm/coproc_a15.c

@@ -114,11 +114,7 @@ static bool access_l2ectlr(struct kvm_vcpu *vcpu,
 
 /*
  * A15-specific CP15 registers.
- * CRn denotes the primary register number, but is copied to the CRm in the
- * user space API for 64-bit register access in line with the terminology used
- * in the ARM ARM.
- * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
- *            registers preceding 32-bit ones.
+ * Important: Must be sorted ascending by CRn, CRM, Op1, Op2
  */
 static const struct coproc_reg a15_regs[] = {
 	/* MPIDR: we use VMPIDR for guest access. */

arch/arm/mach-versatile/include/mach/platform.h

@@ -231,14 +231,12 @@
 /* PCI space */
 #define VERSATILE_PCI_BASE             0x41000000	/* PCI Interface */
 #define VERSATILE_PCI_CFG_BASE	       0x42000000
-#define VERSATILE_PCI_IO_BASE          0x43000000
 #define VERSATILE_PCI_MEM_BASE0        0x44000000
 #define VERSATILE_PCI_MEM_BASE1        0x50000000
 #define VERSATILE_PCI_MEM_BASE2        0x60000000
 /* Sizes of above maps */
 #define VERSATILE_PCI_BASE_SIZE	       0x01000000
 #define VERSATILE_PCI_CFG_BASE_SIZE    0x02000000
-#define VERSATILE_PCI_IO_BASE_SIZE     0x01000000
 #define VERSATILE_PCI_MEM_BASE0_SIZE   0x0c000000	/* 32Mb */
 #define VERSATILE_PCI_MEM_BASE1_SIZE   0x10000000	/* 256Mb */
 #define VERSATILE_PCI_MEM_BASE2_SIZE   0x10000000	/* 256Mb */

arch/arm/mach-versatile/pci.c

@@ -43,9 +43,9 @@
 #define PCI_IMAP0		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x0)
 #define PCI_IMAP1		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x4)
 #define PCI_IMAP2		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x8)
-#define PCI_SMAP0		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
-#define PCI_SMAP1		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
-#define PCI_SMAP2		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x1c)
+#define PCI_SMAP0		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x10)
+#define PCI_SMAP1		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x14)
+#define PCI_SMAP2		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0x18)
 #define PCI_SELFID		__IO_ADDRESS(VERSATILE_PCI_CORE_BASE+0xc)
 
 #define DEVICE_ID_OFFSET		0x00
@@ -170,8 +170,8 @@ static struct pci_ops pci_versatile_ops = {
 	.write	= versatile_write_config,
 };
 
-static struct resource unused_mem = {
-	.name	= "PCI unused",
+static struct resource io_mem = {
+	.name	= "PCI I/O space",
 	.start	= VERSATILE_PCI_MEM_BASE0,
 	.end	= VERSATILE_PCI_MEM_BASE0+VERSATILE_PCI_MEM_BASE0_SIZE-1,
 	.flags	= IORESOURCE_MEM,
@@ -195,17 +195,17 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
 {
 	int ret = 0;
 
-	ret = request_resource(&iomem_resource, &unused_mem);
+	ret = request_resource(&iomem_resource, &io_mem);
 	if (ret) {
-		printk(KERN_ERR "PCI: unable to allocate unused "
+		printk(KERN_ERR "PCI: unable to allocate I/O "
 		       "memory region (%d)\n", ret);
 		goto out;
 	}
 	ret = request_resource(&iomem_resource, &non_mem);
 	if (ret) {
 		printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
 		       "memory region (%d)\n", ret);
-		goto release_unused_mem;
+		goto release_io_mem;
 	}
 	ret = request_resource(&iomem_resource, &pre_mem);
 	if (ret) {
@@ -225,8 +225,8 @@ static int __init pci_versatile_setup_resources(struct pci_sys_data *sys)
 
  release_non_mem:
 	release_resource(&non_mem);
- release_unused_mem:
-	release_resource(&unused_mem);
+ release_io_mem:
+	release_resource(&io_mem);
  out:
 	return ret;
 }
@@ -246,7 +246,7 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 		goto out;
 	}
 
-	ret = pci_ioremap_io(0, VERSATILE_PCI_IO_BASE);
+	ret = pci_ioremap_io(0, VERSATILE_PCI_MEM_BASE0);
 	if (ret)
 		goto out;
 
@@ -294,19 +294,6 @@ int __init pci_versatile_setup(int nr, struct pci_sys_data *sys)
 	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1);
 	__raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2);
 
-	/*
-	 * For many years the kernel and QEMU were symbiotically buggy
-	 * in that they both assumed the same broken IRQ mapping.
-	 * QEMU therefore attempts to auto-detect old broken kernels
-	 * so that they still work on newer QEMU as they did on old
-	 * QEMU. Since we now use the correct (ie matching-hardware)
-	 * IRQ mapping we write a definitely different value to a
-	 * PCI_INTERRUPT_LINE register to tell QEMU that we expect
-	 * real hardware behaviour and it need not be backwards
-	 * compatible for us. This write is harmless on real hardware.
-	 */
-	__raw_writel(0, VERSATILE_PCI_VIRT_BASE+PCI_INTERRUPT_LINE);
-
 	/*
 	 * Do not to map Versatile FPGA PCI device into memory space
 	 */
@@ -340,13 +327,13 @@ static int __init versatile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
 	int irq;
 
-	/*
-	 * Slot	INTA	INTB	INTC	INTD
-	 * 31	PCI1	PCI2	PCI3	PCI0
-	 * 30	PCI0	PCI1	PCI2	PCI3
-	 * 29	PCI3	PCI0	PCI1	PCI2
+	/* slot,  pin,	irq
+	 *  24     1     IRQ_SIC_PCI0
+	 *  25     1     IRQ_SIC_PCI1
+	 *  26     1     IRQ_SIC_PCI2
+	 *  27     1     IRQ_SIC_PCI3
 	 */
-	irq = IRQ_SIC_PCI0 + ((slot + 2 + pin - 1) & 3);
+	irq = IRQ_SIC_PCI0 + ((slot - 24 + pin - 1) & 3);
 
 	return irq;
 }

arch/arm/xen/enlighten.c

@@ -273,15 +273,12 @@ core_initcall(xen_guest_init);
 
 static int __init xen_pm_init(void)
 {
-	if (!xen_domain())
-		return -ENODEV;
-
 	pm_power_off = xen_power_off;
 	arm_pm_restart = xen_restart;
 
 	return 0;
 }
-late_initcall(xen_pm_init);
+subsys_initcall(xen_pm_init);
 
 static irqreturn_t xen_arm_callback(int irq, void *arg)
 {

arch/arm64/kernel/perf_event.c

@@ -375,10 +375,7 @@ validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
 	if (event->pmu != pmu)
 		return 0;
 
-	if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)
-		return 1;
-
-	if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
+	if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
 		return 1;
 
 	armpmu = to_arm_pmu(event->pmu);

arch/mips/ath79/clock.c

@@ -164,7 +164,7 @@ static void __init ar933x_clocks_init(void)
 		ath79_ahb_clk.rate = freq / t;
 	}
 
-	ath79_wdt_clk.rate = ath79_ahb_clk.rate;
+	ath79_wdt_clk.rate = ath79_ref_clk.rate;
 	ath79_uart_clk.rate = ath79_ref_clk.rate;
 }