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Merge pull request efabless#515 from efabless/docs-fix
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Update .readthedocs.yml
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jeffdi authored Nov 13, 2023
2 parents 084af0e + 2a5c603 commit 05baf48
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30 changes: 12 additions & 18 deletions .readthedocs.yml
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@@ -1,28 +1,22 @@
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
# .readthedocs.yml
# .readthedocs.yaml
# Read the Docs configuration file
# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details

# Required
version: 2

# Set the version of Python and other tools you might need
build:
os: ubuntu-22.04
tools:
python: "3.10"

# Build documentation in the docs/ directory with Sphinx
sphinx:
configuration: docs/source/conf.py

conda:
environment: docs/environment.yml
# We recommend specifying your dependencies to enable reproducible builds:
# https://docs.readthedocs.io/en/stable/guides/reproducible-builds.html
python:
install:
- requirements: docs/requirements.txt
1 change: 1 addition & 0 deletions docs/requirements.txt
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Expand Up @@ -6,3 +6,4 @@ sphinx-autobuild
recommonmark
sphinx_markdown_tables
sphinxcontrib-wavedrom
sphinx_rtd_theme
4 changes: 2 additions & 2 deletions manifest
Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ ae07f0d87e69f4dd2026ed841e3a962facac847b verilog/rtl/caravel_openframe.v
d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v
e54c181033aa019f0edcaed5ffc71e54c3888970 verilog/rtl/chip_io.v
1088531d6a69d82b976d4aca7ae923423680a715 verilog/rtl/chip_io_alt.v
e293e138c6e6f5df76db78bdaa34a35003f6ba5f verilog/rtl/chip_io_openframe.v
b080fd6193e1aee1cd476d8a4c117d65ae1e1178 verilog/rtl/chip_io_openframe.v
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
58fd210a64e502fb231d843eada4052f923d788d verilog/rtl/copyright_block.v
Expand All @@ -47,7 +47,7 @@ c96ba94e5779ea6afe452d89632eaada73e26aab verilog/rtl/mprj_io.v
e0c6ead5e35c1ba01d923c482e953c2af9691524 verilog/rtl/mprj_io_buffer.v
3baffde4788f01e2ff0e5cd83020a76bd63ef7d7 verilog/rtl/mprj_logic_high.v
5287821a0ed1994850a978ef0cd024fac51fb6e8 verilog/rtl/open_source.v
33c8fc54298e5425875aaab8c139074ec7d0e9e9 verilog/rtl/openframe_netlists.v
189532aff9e5e2ebbd99befd05cbf50e948b14af verilog/rtl/openframe_netlists.v
b53c154e6acaf44e858c936c8027d0229608676e verilog/rtl/pads.v
669d16642d5dd5f6824812754db20db98c9fe17b verilog/rtl/ring_osc2x13.v
83937790b8f5dbcdd7e9a804b5e9bdf475c0ab7d verilog/rtl/simple_por.v
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