projects: add Synlig

Signed-off-by: Karol Gugala <[email protected]>

projects/project-data-files/synlig.yml

@@ -0,0 +1,32 @@
+# General Information
+name: Systemverilog Netlist Generator (Synlig)
+status: graduated
+brief_summary: Synlig is a SystemVerilog and UHDM front end for Yosys
+website_link: https://github.com/chipsalliance/synlig
+social_media_links: N/A
+project_usage_and_scale: Google, Antmicro, numerous users in open source community
+why_join_chips: To help drive SystemVerilog support in open source ASIC/FPGA tooling
+mission_statement_link: https://github.com/chipsalliance/synlig/blob/main/README.md
+svg_logo_link: https://raw.githubusercontent.com/chipsalliance/synlig/main/images/synlig-logo.svg
+# The primary contact person for the project, will become TSC representative once admitted
+primary_contact:
+  name: Karol Gugala
+  email: [email protected]
+  github_handle: kgugala
+  project_role: Maintainer
+# Contributor & Technical Information
+repositories: https://github.com/chipsalliance/synlig
+issue_tracker_link: https://github.com/chipsalliance/synlig/issues
+active_committers: https://github.com/chipsalliance/synlig/graphs/contributors
+release_methodology: Rolling releases on GitHub for every commit passing tests on the main branch
+communication_channels: "CHIPS Alliance Slack channels, GitHub Issues"
+# Legal Informantion
+license: Apache-2.0
+financial_sponsorship: N/A
+accepted_lf_code_of_conduct: yes
+adopted_chips_alliance_ip_policy: yes
+chips_header_footer_text_on_website: yes
+trademarks_and_domains_transferred_to_lf: yes
+security_vulnerabilities_reporting_process: The project will use [CHIPS Alliance's default security policy](https://github.com/chipsalliance/tsc#reporting-security-vulnerabilities)
+# (For specifications only) link to reference implementation of the specification, N/A for non-spec projects
+spec_public_reference_implementation: N/A