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Build(deps): Bump third_party/black_parrot_sdk from f92dc46 to e2637ea #6056

Build(deps): Bump third_party/black_parrot_sdk from f92dc46 to e2637ea

Build(deps): Bump third_party/black_parrot_sdk from f92dc46 to e2637ea #6056

Triggered via pull request November 22, 2024 07:59
Status Success
Total duration 1h 1m 13s
Artifacts 49

main.yml

on: pull_request
Matrix: build-binaries
Emit Workflow Info
0s
Emit Workflow Info
Style check
1m 36s
Style check
Verify README Correctness (Installation From Sources)
41m 59s
Verify README Correctness (Installation From Sources)
Matrix: Large Designs Tests / opentitan_parse_report
Matrix: Parsing Tests / parsing-tests
Large Designs Tests  /  Ibex (Vivado synthesis)
6m 32s
Large Designs Tests / Ibex (Vivado synthesis)
Large Designs Tests  /  Ibex (F4PGA synthesis)
10m 56s
Large Designs Tests / Ibex (F4PGA synthesis)
Large Designs Tests  /  Opentitan 9d82960888 (synthesis)
34m 45s
Large Designs Tests / Opentitan 9d82960888 (synthesis)
Large Designs Tests  /  Opentitan (synthesis)
50m 31s
Large Designs Tests / Opentitan (synthesis)
Large Designs Tests  /  VeeR-EH1 (synthesis)
5m 30s
Large Designs Tests / VeeR-EH1 (synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) FPGA synthesis)
16m 3s
Large Designs Tests / Black Parrot (AMD (Xilinx) FPGA synthesis)
Large Designs Tests  /  Black Parrot (ASIC synthesis)
42m 39s
Large Designs Tests / Black Parrot (ASIC synthesis)
Large Designs Tests  /  Black Parrot (AMD (Xilinx) with PySynlig)
39m 37s
Large Designs Tests / Black Parrot (AMD (Xilinx) with PySynlig)
Diff generated BSG Micro Designs tests  /  Parse and diff BSG Micro Designs
6m 4s
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Matrix: Formal Verification Tests / tests-formal-verification
Parsing Tests  /  Generate AST diff
2m 0s
Parsing Tests / Generate AST diff
Parsing Tests  /  Summary Generation
1m 35s
Parsing Tests / Summary Generation
Release Package
0s
Release Package
Verify README Correctness (Download And Run Release)
0s
Verify README Correctness (Download And Run Release)
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4 warnings
Large Designs Tests / VeeR-EH1 (synthesis)
No files were found with the provided path: tests/build/chipsalliance.org_cores_VeeR_EH1_1.9/synth-vivado/chipsalliance.org_cores_VeeR_EH1_1.9.edif. No artifacts will be uploaded.
Diff generated BSG Micro Designs tests / Parse and diff BSG Micro Designs
Some generated tests differ from the reference or were not generated at all. Check the test statuses in the workflow summary or `bsg_micro_designs_summary.md` in the artifacts.
Large Designs Tests / Black Parrot (ASIC synthesis)
No files were found with the provided path: build third_party/OpenROAD-flow-scripts/logs third_party/OpenROAD-flow-scripts/reports third_party/OpenROAD-flow-scripts/results. No artifacts will be uploaded.
Large Designs Tests / Opentitan (synthesis)
No files were found with the provided path: tests/build/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1/synth-yosys/lowrisc_systems_custom_tiny_chip_custom_tiny_nexysvideo_0.1.edif. No artifacts will be uploaded.

Artifacts

Produced during runtime
Name Size
binaries-asan
292 MB
binaries-package
23.1 MB
binaries-plugin
41.6 MB
binaries-pysynlig
652 MB
binaries-release
41.8 MB
bp_e_bp_unicore_cfg.edif
3.9 MB
bsg-logs
5.56 MB
bsg-outputs
1.72 MB
formal-verification-logs-simple
18.5 MB
formal-verification-logs-sv2v
63.1 MB
formal-verification-logs-yosys
50.3 MB
lowrisc_ibex_top_artya7_surelog_0.1.bit
105 KB
lowrisc_systems_top_earlgrey_nexysvideo_0.1.bit
616 KB
opentitan-logs-full
5.07 MB
opentitan-logs-quick
1.52 MB
plots_binaries-asan
54.2 KB
plots_binaries-package
32.3 KB
plots_binaries-plugin
31.6 KB
plots_binaries-pysynlig
68.1 KB
plots_binaries-release
31.3 KB
plots_blackparrot_synth_asic
254 KB
plots_blackparrot_synth_xilinx
104 KB
plots_blackparrot_synth_xilinx_python
231 KB
plots_build_tools
80 KB
plots_formal_verification_simple
114 KB
plots_formal_verification_sv2v
116 KB
plots_formal_verification_yosys
97.7 KB
plots_ibex_synth
48.1 KB
plots_ibex_synth_f4pga
78.3 KB
plots_opentitan_9d82960888_synth
196 KB
plots_opentitan_parse_report_full
84.9 KB
plots_opentitan_parse_report_quick
42.2 KB
plots_opentitan_synth
277 KB
plots_tests_asan_read_systemverilog
226 KB
plots_tests_asan_read_uhdm
164 KB
plots_tests_plugin_read_systemverilog
36.9 KB
plots_tests_plugin_read_uhdm
32.9 KB
plots_tests_release_read_systemverilog
39.1 KB
plots_tests_release_read_uhdm
32.4 KB
plots_veer_synth
37.7 KB
python_bp_e_bp_unicore_cfg.edif
3.9 MB
results_parsing_tests_asan_read_systemverilog Expired
1.6 MB
results_parsing_tests_asan_read_uhdm Expired
1.81 MB
results_parsing_tests_plugin_read_systemverilog Expired
1.53 MB
results_parsing_tests_plugin_read_uhdm Expired
1.78 MB
results_parsing_tests_release_read_systemverilog Expired
1.49 MB
results_parsing_tests_release_read_uhdm Expired
1.73 MB
tools
39.1 MB
top_artya7.bit
121 KB