The new decoder #3534
The new decoder #3534
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TODO: need - release version of chisel 3.6.1, 5.1 - Zb/Zbk support - riscv-opcode path configurable
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some TODO need to be resolved, other LGTM(since I wrote it).
Need review by @jerryz123
| @@ -7,3 +7,9 @@ | |||
| [submodule "dependencies/chisel"] | |||
| path = dependencies/chisel | |||
| url = https://github.com/chipsalliance/chisel.git | |||
| [submodule "dependencies/rvdecoderdb"] | |||
| path = dependencies/rvdecoderdb | |||
| url = https://github.com/sequencer/rvdecoderdb.git | |||
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After @jerryz123 approves, I will transfer this repo to chipsalliance.
| // TODO: configurable | ||
| (org.chipsalliance.rvdecoderdb.fromFile.instructions(os.pwd / "dependencies" / "riscv-opcodes") ++ |
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can you fixup this TODO? with out configuring it, downstream users cannot use it.
| @@ -199,7 +199,7 @@ class InstructionDecoder(p: InstructionDecoderParameter) { | |||
| override def name: String = "rxs2" | |||
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| override def genTable(op: RocketDecodePattern): BitPat = op.instruction.name match { | |||
| case i if Seq("bne", "beq", "blt", "bltu", "bge", "bgeu", "sb", "sh", "sw", "add", "sub", "slt", "sltu", "and", "or", "xor", "sll", "srl", "sra", "czero.eqz", "czero.nez", "sfence.vma", "hfence.vvma", "hfence.gvma", "hsv.b", "hsv.h", "hsv.w", "sd", "addw", "subw", "sllw", "srlw", "sraw", "hsv.d", "mul", "mulh", "mulhu", "mulhsu", "div", "divu", "rem", "remu", "mulw", "divw", "divuw", "remw", "remuw", "amoadd.w", "amoxor.w", "amoswap.w", "amoand.w", "amoor.w", "amomin.w", "amominu.w", "amomax.w", "amomaxu.w", "lr.w", "sc.w", "amoadd.d", "amoswap.d", "amoxor.d", "amoand.d", "amoor.d", "amomin.d", "amominu.d", "amomax.d", "amomaxu.d", "lr.d", "sc.d", "custom0.rs1.rs2", "custom0.rd.rs1.rs2", "custom1.rs1.rs2", "custom1.rd.rs1.rs2", "custom2.rs1.rs2", "custom2.rd.rs1.rs2", "custom3.rs1.rs2", "custom3.rd.rs1.rs2").contains(i) => y | |||
| case i if Seq("amomaxu.w", "amoand.w", "amoor.w", "amoxor.w", "amoswap.w", "lr.w", "amomax.w", "amoadd.w", "amomin.w", "amominu.w", "sc.w", "lr.d", "amomax.d", "amoswap.d", "amoxor.d", "amoand.d", "amomin.d", "amoor.d", "amoadd.d", "amomaxu.d", "amominu.d", "sc.d", "hsv.w", "hsv.b", "hfence.vvma", "hsv.h", "hfence.gvma", "hsv.d", "or", "srl", "sltu", "sra", "sb", "add", "xor", "beq", "bge", "sw", "blt", "bgeu", "bltu", "bne", "sub", "and", "slt", "sh", "sll", "addw", "sd", "sllw", "sraw", "subw", "srlw", "mulhsu", "rem", "div", "mul", "mulhu", "mulh", "remu", "divu", "remuw", "divw", "divuw", "mulw", "remw", "sfence.vma", "czero.nez", "czero.eqz", "custom0.rs1.rs2", "custom0.rd.rs1.rs2", "custom1.rs1.rs2", "custom1.rd.rs1.rs2", "custom2.rs1.rs2", "custom2.rd.rs1.rs2", "custom3.rs1.rs2", "custom3.rd.rs1.rs2").contains(i) => y | |||
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How about split them with '\n'
I don’t think the reason keeping the original IntCtrl is a good design since for different instruction sets, some control signal will be optional. The current design doesn’t support it.
i don’t think the maintain burden is acceptable for me :( |
I don't like the premise that additional extensions require adding signals to IntCtrlSigs. IntCtrlSigs are the control signals for the subset of the control signals for the base integer ISA... the fields in this bundle should never need to change. We should develop interfaces and APIs that allow for extensions to define their own control signal bundles that propagate through the pipeline.
Aggressively deprecating APIs is a large maintenance burden. I don't see how retaining support for the original decoder is a large burden, if we do it with the correct interfaces. Once done, the original decoder code should never need to change again. I will look into integrating this without deprecating the existing decoder. |
This PR takes over #3498 and removed Zb* and Zk* since #3532 has been merged.
Related issue: #3498
Type of change: other enhancement
Impact: API addition (no impact on existing code)
Development Phase: implementation
Release Notes
Switch to DecodeTable API.