- Zcb Instructions with `OP[1:0] = 2'b0` added.
- These are Compressed version of following I-type instructins.
	- lbu
	- lhu
	- lh
	- sb
	- sh
- These instructions lies in Quadrant 0 based on compressed Opcode.

Signed-off-by: Abdul Wadood <[email protected]>

- Implement the 16 to 32 bit Decoder for `Zcb` Instructions having OP[1:0] == 00
- This decodes the following compressed instructions into its 32-bit equivalent instructions.
	c.lbu, c.lhu, c.lh, c.cb, c.sh

Signed-off-by: Abdul Wadood <[email protected]>

- Zcb Instructions with `OP[1:0] = 2'b01` added.
- These instructions lies in Q1 of Compressed Instructions.

Signed-off-by: Abdul Wadood <[email protected]>

- Implement the 16 to 32 bit Decoder for `Zcb` Instructions having OP[1:0] = 2'b01
- The 16 bit -> 32 bit instruction mapping is given as follows:
	c.zext.b -> andi
	c.sext.b -> sext.b   (require Zbb)
	c.zext.h -> zext.h   (require Zbb)
	c.sext.h -> sext.h   (require Zbb)
	c.zext.w -> add.uw   (require Zba, only for RV64)
	c.not    -> xori
	c.mul    -> mul      (Require M standard extension)

Signed-off-by: Abdul Wadood <[email protected]>

- Added `usingCompressedSuiteB` to enable/disable `Zcb` extension.
- This parameter depends upon existing `usingCompressed` parameter.
- By default `Zcb` is disable in RocketCore.
- Passed this parameter along with `usingBitManip` and `usingMulDiv` to RVCDecoder enable/disable the decoding of corresponding `Zcb` instructions.

Signed-off-by: Abdul Wadood <[email protected]>

Signed-off-by: Abdul Wadood <[email protected]>

Signed-off-by: Abdul Wadood <[email protected]>

Signed-off-by: Abdul Wadood <[email protected]>