Merge pull request #3323 from chipsalliance/mergify/bp/master/pr-3322

Fix no-debug-node designs (backport #3322)

src/main/scala/devices/debug/Periphery.scala

@@ -14,7 +14,7 @@ import freechips.rocketchip.jtag._
 import freechips.rocketchip.util._
 import freechips.rocketchip.prci.{ClockSinkParameters, ClockSinkNode}
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.interrupts.{NullIntSyncSource}
+import freechips.rocketchip.interrupts.{NullIntSyncSource, IntSyncXbar}
 
 /** Protocols used for communicating with external debugging tools */
 sealed trait DebugExportProtocol
@@ -99,7 +99,7 @@ trait HasPeripheryDebug { this: BaseSubsystem =>
     tlDM
   }
 
-  lazy val debugNode = debugOpt.map(_.intnode).getOrElse(NullIntSyncSource())
+  lazy val debugNode = debugOpt.map(_.intnode).getOrElse(IntSyncXbar() := NullIntSyncSource())
 
   val psd = InModuleBody {
     val psd = IO(new PSDIO)

src/main/scala/interrupts/Nodes.scala

@@ -87,3 +87,11 @@ case class IntSyncSinkNode(sync: Int)(implicit valName: ValName)
 {
   override lazy val nodedebugstring = s"sync:${sync}"
 }
+
+case class IntSyncNexusNode(
+  sourceFn:       Seq[IntSourcePortParameters] => IntSourcePortParameters,
+  sinkFn:         Seq[IntSinkPortParameters]   => IntSinkPortParameters,
+  inputRequiresOutput: Boolean = true,
+  outputRequiresInput: Boolean = true)(
+  implicit valName: ValName)
+  extends NexusNode(IntSyncImp)(sourceFn, sinkFn, inputRequiresOutput, outputRequiresInput) with IntFormatNode

src/main/scala/interrupts/Xbar.scala

@@ -25,9 +25,36 @@ class IntXbar()(implicit p: Parameters) extends LazyModule
   }
 }
 
+class IntSyncXbar()(implicit p: Parameters) extends LazyModule
+{
+  val intnode = new IntSyncNexusNode(
+    sinkFn         = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
+    sourceFn       = { seq =>
+      IntSourcePortParameters((seq zip seq.map(_.num).scanLeft(0)(_+_).init).map {
+        case (s, o) => s.sources.map(z => z.copy(range = z.range.offset(o)))
+      }.flatten)
+    })
+  {
+    override def circuitIdentity = outputs == 1 && inputs == 1
+  }
+
+  lazy val module = new Impl
+  class Impl extends LazyModuleImp(this) {
+    val cat = intnode.in.map { case (i, e) => i.sync.take(e.source.num) }.flatten
+    intnode.out.foreach { case (o, _) => o.sync := cat }
+  }
+}
+
 object IntXbar {
-  def apply(implicit p: Parameters): IntNode = {
+  def apply()(implicit p: Parameters): IntNode = {
     val xbar = LazyModule(new IntXbar)
     xbar.intnode
   }
 }
+
+object IntSyncXbar {
+  def apply()(implicit p: Parameters): IntSyncNode = {
+    val xbar = LazyModule(new IntSyncXbar)
+    xbar.intnode
+  }
+}

src/main/scala/subsystem/HasTiles.scala

@@ -205,15 +205,15 @@ trait HasTileInputConstants extends InstantiatesTiles { this: BaseSubsystem =>
   * They need to be instantiated before tiles are attached to the subsystem containing them.
   */
 trait HasTileNotificationSinks { this: LazyModule =>
-  val tileHaltXbarNode = IntXbar(p)
+  val tileHaltXbarNode = IntXbar()
   val tileHaltSinkNode = IntSinkNode(IntSinkPortSimple())
   tileHaltSinkNode := tileHaltXbarNode
 
-  val tileWFIXbarNode = IntXbar(p)
+  val tileWFIXbarNode = IntXbar()
   val tileWFISinkNode = IntSinkNode(IntSinkPortSimple())
   tileWFISinkNode := tileWFIXbarNode
 
-  val tileCeaseXbarNode = IntXbar(p)
+  val tileCeaseXbarNode = IntXbar()
   val tileCeaseSinkNode = IntSinkNode(IntSinkPortSimple())
   tileCeaseSinkNode := tileCeaseXbarNode
 }