fixup! [major] Add public modules

abi.md

@@ -54,8 +54,8 @@ resolve the name.
 
 ### Public Modules
 
-Any public modules shall be implemented in Verilog in a consistent way.  Any
-public module shall exist as a Verilog module of the same name.  Each public
+All public modules shall be implemented in Verilog in a consistent way.  All
+public modules shall exist as Verilog modules of the same name.  Each public
 module shall be placed in a file with a format as follows where `module` is the
 name of the public module:
 

spec.md

@@ -147,7 +147,9 @@ circuit MyTop...
 A FIRRTL circuit is a named collection of FIRRTL modules.  Each module is a
 hardware "unit" that has ports, registers, wires, and may instantiate other
 modules (see: [@sec:modules]).  (This is the same concept as a Verilog
-`module`{.verilog}.)  A public module is usable outside of the current circuit.
+`module`{.verilog}.)  A public module may be instantiated outside the current
+circuit.  Public modules are the exported identifiers of a circuit.  Any
+non-public module may not be instantiated outside the current circuit.
 
 Consider the following circuit named `Foo`.  This contains two modules, `Bar`
 and `Baz`.  Module `Baz` is marked public.
@@ -221,9 +223,7 @@ instance statement for details on how to instantiate a module
 ### Public Modules
 
 A public module is a module that is marked with the `public`{.firrtl} keyword.
-A public module has a defined ABI---knowing the FIRRTL representation is
-sufficient to know its compiled representation.  This means that a public module
-is available external to this circuit.
+A public module may be instantiated outside by other circuits.
 
 The example below shows a public module `Foo`:
 
@@ -243,8 +243,8 @@ A public module has a number of restrictions:
 1. A `RWProbe`{.firrtl} may not be used to access a public module's ports.
 1. A public module's ports are lowered using one of the port lowering ABIs
    defined in the FIRRTL ABI specification.
-1. A public module may be instantiated by other modules, but must be compiled
-   without information from its instantiating context.
+1. A public module may be instantiated by other modules within a circuit, but
+   the behavior of the module must not be affected by these instantiations.
 
 The last point requires clarification.  A public module may or may not be
 instantiated by other modules in a circuit.  Regardless of whether or not it is