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Remove Path from SRAMDescription as it isn't fully functional #4381

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Sep 4, 2024
Merged

Remove Path from SRAMDescription as it isn't fully functional #4381

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2 changes: 0 additions & 2 deletions src/main/scala/chisel3/util/SRAM.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -92,7 +92,6 @@ final class SRAMDescription extends Bundle {
val write: Property[Int] = Property[Int]()
val readwrite: Property[Int] = Property[Int]()
val maskGranularity: Property[Int] = Property[Int]()
val hierarchy: Property[Path] = Property[Path]()
}

/** A IO bundle of signals connecting to the ports of a memory, as requested by
Expand Down Expand Up @@ -591,7 +590,6 @@ object SRAM {
})
.getOrElse(0)
)
description.hierarchy := Property(Path(mem))

_out
}
Expand Down
15 changes: 6 additions & 9 deletions src/test/scala/chiselTests/util/SRAMSpec.scala
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Expand Up @@ -37,7 +37,7 @@ class SRAMSpec extends ChiselFlatSpec {
val chirrtl = chirrtlCircuit.serialize
chirrtl should include("module Top :")
chirrtl should include(
"wire sram : { readPorts : { flip address : UInt<5>, flip enable : UInt<1>, data : UInt<8>}[0], writePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip data : UInt<8>}[0], readwritePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>, flip writeData : UInt<8>}[1], description : { depth : Integer, dataWidth : Integer, masked : Bool, read : Integer, write : Integer, readwrite : Integer, maskGranularity : Integer, hierarchy : Path}"
"wire sram : { readPorts : { flip address : UInt<5>, flip enable : UInt<1>, data : UInt<8>}[0], writePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip data : UInt<8>}[0], readwritePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>, flip writeData : UInt<8>}[1], description : { depth : Integer, dataWidth : Integer, masked : Bool, read : Integer, write : Integer, readwrite : Integer, maskGranularity : Integer}"
)
chirrtl should include("mem sram_sram")
chirrtl should include("data-type => UInt<8>")
Expand All @@ -52,9 +52,6 @@ class SRAMSpec extends ChiselFlatSpec {
chirrtl should include("connect sram.readwritePorts[0].readData, sram_sram.RW0.rdata")
chirrtl should include("connect sram_sram.RW0.wdata, sram.readwritePorts[0].writeData")
chirrtl should include("connect sram_sram.RW0.wmode, sram.readwritePorts[0].isWrite")
chirrtl should include(
"""propassign sram.description.hierarchy, path("OMReferenceTarget:~Top|Top>sram_sram")"""
)

val dummyAnno = annos.collectFirst { case DummyAnno(t) => (t.toString) }
dummyAnno should be(Some("~Top|Top>sram_sram"))
Expand All @@ -81,7 +78,7 @@ class SRAMSpec extends ChiselFlatSpec {
chirrtl should include("module Top :")
chirrtl should include("mem carrot :")
chirrtl should include(
"wire sramInterface : { readPorts : { flip address : UInt<5>, flip enable : UInt<1>, data : UInt<8>}[0], writePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip data : UInt<8>}[0], readwritePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>, flip writeData : UInt<8>}[1], description : { depth : Integer, dataWidth : Integer, masked : Bool, read : Integer, write : Integer, readwrite : Integer, maskGranularity : Integer, hierarchy : Path}"
"wire sramInterface : { readPorts : { flip address : UInt<5>, flip enable : UInt<1>, data : UInt<8>}[0], writePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip data : UInt<8>}[0], readwritePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>, flip writeData : UInt<8>}[1], description : { depth : Integer, dataWidth : Integer, masked : Bool, read : Integer, write : Integer, readwrite : Integer, maskGranularity : Integer}"
)

val dummyAnno = annos.collectFirst { case DummyAnno(t) => (t.toString) }
Expand Down Expand Up @@ -234,20 +231,20 @@ class SRAMSpec extends ChiselFlatSpec {
it should "be possible to access SRAM description information" in {

class Top extends Module {
val sramPath = IO(Output(Property[Path]()))
val size = IO(Output(Property[Int]()))
val sram = SRAM(
size = 32,
tpe = UInt(8.W),
numReadPorts = 0,
numWritePorts = 0,
numReadwritePorts = 1
)
sramPath := sram.description.get.hierarchy
size := sram.description.get.depth
}
// TODO we need a way with ChiselSim to evaluate properties
val chirrtl = emitCHIRRTL(new Top)
chirrtl should include("output sramPath : Path")
chirrtl should include("propassign sramPath, sram.description.hierarchy")
chirrtl should include("output size : Integer")
chirrtl should include("propassign size, sram.description.depth")
}

it should "be possible to create an SramInterface Wire" in {
Expand Down