upgrade baa, fst-writer and fraction dependencies (#2382)

calyxir · Dec 19, 2024 · e0b02ed · e0b02ed
1 parent 37d90d9
commit e0b02ed
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Showing 8 changed files with 116 additions and 123 deletions.
diff --git a/Cargo.lock b/Cargo.lock
diff --git a/Cargo.toml b/Cargo.toml
@@ -58,6 +58,7 @@ calyx-ir = { path = "calyx-ir", version = "0.7.1" }
 calyx-frontend = { path = "calyx-frontend", version = "0.7.1" }
 calyx-opt = { path = "calyx-opt", version = "0.7.1" }
 calyx-backend = { path = "calyx-backend", version = "0.7.1" }
+baa = { version = "0.16.0", features = ["bigint", "serde1", "fraction1"] }
 
 [workspace.dependencies.petgraph]
 version = "0.6"

diff --git a/cider-dap/Cargo.toml b/cider-dap/Cargo.toml
@@ -15,7 +15,7 @@ argh = "0.1"
 slog = "2.7.0"
 slog-term = "2.8.0"
 slog-async = "2.7.0"
-baa = "0.14"
+baa.workspace = true
 
 cider = { path = "../cider" }
 

diff --git a/cider/Cargo.toml b/cider/Cargo.toml
@@ -21,10 +21,9 @@ pest_derive.workspace = true
 pest_consume.workspace = true
 argh.workspace = true
 owo-colors = "^3.5"
-bitvec = "1.0"
 serde_json = "1.0"
 rustyline = "=10.0.0"
-fraction = { version = "0.11.0", features = ["with-serde-support"] }
+fraction = { version = "0.15.3", features = ["with-serde-support"] }
 thiserror = "1.0.26"
 slog = "2.7.0"
 slog-term = "2.8.0"
@@ -33,7 +32,6 @@ ahash = "0.8.3"
 num-bigint = "0.4.6"
 num-traits = "0.2.19"
 
-once_cell = "1.9.0"
 petgraph = "0.6.3"
 
 calyx-ir = { path = "../calyx-ir" }
@@ -42,8 +40,8 @@ calyx-opt = { path = "../calyx-opt" }
 calyx-frontend = { path = "../calyx-frontend" }
 
 ciborium = "0.2.2"
-baa = { version = "0.14.0", features = ["bigint", "serde1", "fraction1"] }
-fst-writer = "0.2.1"
+baa.workspace = true
+fst-writer = "0.2.3"
 bon = "2.3"
 
 [dev-dependencies]

diff --git a/cider/src/flatten/flat_ir/base.rs b/cider/src/flatten/flat_ir/base.rs
@@ -565,7 +565,7 @@ impl AssignedValue {
     /// A utility constructor which returns a new implicitly assigned value with
     /// a one bit high value
     pub fn implicit_bit_high() -> Self {
-        Self::new(BitVecValue::tru(), AssignmentWinner::Implicit)
+        Self::new(BitVecValue::new_true(), AssignmentWinner::Implicit)
     }
 
     /// A utility constructor which returns an [`AssignedValue`] with the given
@@ -586,13 +586,13 @@ impl AssignedValue {
     /// high value and a [`AssignmentWinner::Cell`] as the winner
     #[inline]
     pub fn cell_b_high() -> Self {
-        Self::cell_value(BitVecValue::tru())
+        Self::cell_value(BitVecValue::new_true())
     }
     /// A utility constructor which returns an [`AssignedValue`] with a one bit
     /// low value and a [`AssignmentWinner::Cell`] as the winner
     #[inline]
     pub fn cell_b_low() -> Self {
-        Self::cell_value(BitVecValue::fals())
+        Self::cell_value(BitVecValue::new_false())
     }
 
     pub fn thread(&self) -> Option<ThreadIdx> {

diff --git a/cider/src/flatten/primitives/stateful/math.rs b/cider/src/flatten/primitives/stateful/math.rs
@@ -49,9 +49,9 @@ impl<const DEPTH: usize> Primitive for StdMultPipe<DEPTH> {
         let done_signal = port_map.insert_val_general(
             done,
             AssignedValue::cell_value(if self.done_is_high {
-                BitVecValue::tru()
+                BitVecValue::new_true()
             } else {
-                BitVecValue::fals()
+                BitVecValue::new_false()
             }),
         )?;
 
@@ -101,9 +101,9 @@ impl<const DEPTH: usize> Primitive for StdMultPipe<DEPTH> {
         port_map.insert_val_general(
             done,
             AssignedValue::cell_value(if self.done_is_high {
-                BitVecValue::tru()
+                BitVecValue::new_true()
             } else {
-                BitVecValue::fals()
+                BitVecValue::new_false()
             }),
         )?;
 
@@ -378,9 +378,9 @@ impl<const DEPTH: usize> Primitive for FxpMultPipe<DEPTH> {
         let done_signal = port_map.insert_val_general(
             done,
             AssignedValue::cell_value(if self.done_is_high {
-                BitVecValue::tru()
+                BitVecValue::new_true()
             } else {
-                BitVecValue::fals()
+                BitVecValue::new_false()
             }),
         )?;
 
@@ -439,9 +439,9 @@ impl<const DEPTH: usize> Primitive for FxpMultPipe<DEPTH> {
         port_map.insert_val_general(
             done,
             AssignedValue::cell_value(if self.done_is_high {
-                BitVecValue::tru()
+                BitVecValue::new_true()
             } else {
-                BitVecValue::fals()
+                BitVecValue::new_false()
             }),
         )?;
         port_map.write_exact_unchecked(out, self.current_output.clone());

diff --git a/cider/src/flatten/primitives/stateful/memories.rs b/cider/src/flatten/primitives/stateful/memories.rs
@@ -76,7 +76,7 @@ impl Primitive for StdReg {
                 BitVecValue::zero(self.internal_state.value.width());
             port_map.insert_val_general(
                 done,
-                AssignedValue::cell_value(BitVecValue::fals()),
+                AssignedValue::cell_value(BitVecValue::new_false()),
             )?
         } else if port_map[write_en].as_bool().unwrap_or_default() {
             self.internal_state.value = port_map[input]
@@ -89,13 +89,13 @@ impl Primitive for StdReg {
 
             port_map.insert_val_general(
                 done,
-                AssignedValue::cell_value(BitVecValue::tru()),
+                AssignedValue::cell_value(BitVecValue::new_true()),
             )?
         } else {
             self.done_is_high = false;
             port_map.insert_val_general(
                 done,
-                AssignedValue::cell_value(BitVecValue::fals()),
+                AssignedValue::cell_value(BitVecValue::new_false()),
             )?
         };
 
@@ -120,9 +120,9 @@ impl Primitive for StdReg {
         let done_signal = port_map.insert_val_general(
             done,
             AssignedValue::cell_value(if self.done_is_high {
-                BitVecValue::tru()
+                BitVecValue::new_true()
             } else {
-                BitVecValue::fals()
+                BitVecValue::new_false()
             }),
         )?;
 
@@ -566,9 +566,9 @@ impl Primitive for CombMem {
         let done_signal = port_map.insert_val_general(
             self.done(),
             AssignedValue::cell_value(if self.done_is_high {
-                BitVecValue::tru()
+                BitVecValue::new_true()
             } else {
-                BitVecValue::fals()
+                BitVecValue::new_false()
             }),
         )?;
         Ok(done_signal | read)
@@ -902,9 +902,9 @@ impl Primitive for SeqMem {
         let done_signal = port_map.insert_val_general(
             self.done(),
             AssignedValue::cell_value(if self.done_is_high {
-                BitVecValue::tru()
+                BitVecValue::new_true()
             } else {
-                BitVecValue::fals()
+                BitVecValue::new_false()
             }),
         )?;
 
@@ -962,9 +962,9 @@ impl Primitive for SeqMem {
         port_map.insert_val_general(
             self.done(),
             AssignedValue::cell_value(if self.done_is_high {
-                BitVecValue::tru()
+                BitVecValue::new_true()
             } else {
-                BitVecValue::fals()
+                BitVecValue::new_false()
             }),
         )?;
         port_map.write_exact_unchecked(

diff --git a/cider/src/flatten/structures/environment/env.rs b/cider/src/flatten/structures/environment/env.rs
@@ -151,9 +151,9 @@ impl PortMap {
         self.insert_val(
             target,
             AssignedValue::cell_value(if done_bool {
-                BitVecValue::tru()
+                BitVecValue::new_true()
             } else {
-                BitVecValue::fals()
+                BitVecValue::new_false()
             }),
         )
         .map_err(|e| RuntimeError::ConflictingAssignments(e).into())
@@ -1687,7 +1687,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> {
             + self.env.ctx.as_ref().primary[ledger.comp_id]
                 .unwrap_standard()
                 .go;
-        self.env.ports[go] = PortValue::new_implicit(BitVecValue::tru());
+        self.env.ports[go] = PortValue::new_implicit(BitVecValue::new_true());
     }
 
     // may want to make this iterate directly if it turns out that the vec
@@ -1867,7 +1867,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> {
 
         for (comp, id) in self.env.pc.finished_comps() {
             let done_port = self.env.unwrap_comp_done(*comp);
-            let v = PortValue::new_implicit(BitVecValue::tru());
+            let v = PortValue::new_implicit(BitVecValue::new_true());
             self.env.ports[done_port] = if self.conf.check_data_race {
                 v.with_thread(id.expect("finished comps should have a thread"))
             } else {
@@ -1902,7 +1902,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> {
             // if the done is not high & defined, we need to set it to low
             if !self.env.ports[comp_done].as_bool().unwrap_or_default() {
                 self.env.ports[comp_done] =
-                    PortValue::new_implicit(BitVecValue::fals());
+                    PortValue::new_implicit(BitVecValue::new_false());
             }
 
             match &ctx_ref.primary[node.control_node_idx] {
@@ -1917,7 +1917,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> {
                     // set go high
                     let go_idx = index_bases + go_local;
                     self.env.ports[go_idx] =
-                        PortValue::new_implicit(BitVecValue::tru());
+                        PortValue::new_implicit(BitVecValue::new_true());
                 }
                 ControlNode::Invoke(invoke) => {
                     if invoke.comb_group.is_some()
@@ -1931,7 +1931,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> {
 
                     let go = self.get_global_port_idx(&invoke.go, node.comp);
                     self.env.ports[go] =
-                        PortValue::new_implicit(BitVecValue::tru())
+                        PortValue::new_implicit(BitVecValue::new_true())
                             .with_thread_optional(
                                 if self.conf.check_data_race {
                                     assert!(thread.is_some(), "Invoke is running but has no thread. This shouldn't happen. In {}", node.comp.get_full_name(&self.env));