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remove useless use of format
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jiahanxie353 committed Jan 5, 2025
1 parent 7ae26b0 commit 1d6ff18
Showing 1 changed file with 1 addition and 3 deletions.
4 changes: 1 addition & 3 deletions calyx-backend/src/verilog.rs
Original file line number Diff line number Diff line change
Expand Up @@ -404,9 +404,7 @@ impl Backend for VerilogBackend {
true, // By default, propagate defines from first files to the following files
false, // By default, keep the time units
)
.map_err(|err| {
Error::write_error(format!("{}", err.to_string()))
})?;
.map_err(|err| Error::write_error(format!("{}", err)))?;
}
// Rewind to the start of the temporary file so that we can read the content
temp_writer.seek(SeekFrom::Start(0)).map_err(|_| {
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