Fix strange opcodes

broxus · Oct 25, 2023 · 11da70a · 11da70a
1 parent 3f4502d
commit 11da70a
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Showing 8 changed files with 73 additions and 25 deletions.
diff --git a/Cargo.lock b/Cargo.lock
diff --git a/Cargo.toml b/Cargo.toml
@@ -2,7 +2,7 @@
 name = "everscale-asm"
 description = "Rust implementation of TVM Assembler"
 repository = "https://github.com/broxus/everscale-asm"
-version = "0.0.3"
+version = "0.0.4"
 edition = "2021"
 rust-version = "1.70"
 include = ["src/**/*.rs", "src/**/*.tvm", "./LICENSE-*", "./README.md"]

diff --git a/README.md b/README.md
@@ -12,7 +12,7 @@
 
 [rust-version-link]: https://blog.rust-lang.org/2023/06/01/Rust-1.70.0.html
 
-[workflow-badge]: https://img.shields.io/github/actions/workflow/status/broxus/everscale-asm/master.yml?branch=master
+[workflow-badge]: https://img.shields.io/github/actions/workflow/status/broxus/everscale-asm/master.yaml?branch=master
 
 [workflow-link]: https://github.com/broxus/everscale-asm/actions?query=workflow%3Amaster
 
@@ -63,6 +63,45 @@ let code: Cell = Code::assemble(r#"
 "#)?;
 ```
 
+## Syntax
+
+```
+// Single-line comments
+
+// Opcodes must be in uppercase, can start with a digit or minus,
+// and can contain '#' or '_'
+NOP
+2DROP
+-ROT
+STREF_L
+
+// Opcodes with number as an argument
+PUSHINT 12
+PUSHINT -0xded
+PUSHINT 0b10110101
+
+// Opcodes with stack register as an argument
+PUSH s1
+XCHG s10, s100
+PU2XC s1, s(-1), s(-2)
+
+// Opcodes with control registers (c0, .., c5, c7)
+PUSH c3
+PUSHCTR c7
+
+// Opcodes with slice or continuation
+PUSHSLICE x{123123_}
+PUSHSLICE b{10001001}
+IFREFELSEREF {
+  PUSHINT 1
+}, {
+  PUSHINT 2
+}
+
+```
+
+[Full opcodes list](https://test.ton.org/tvm.pdf)
+
 ## Contributing
 
 We welcome contributions to the project! If you notice any issues or errors, feel free to open an issue or submit a pull request.

diff --git a/cli/Cargo.toml b/cli/Cargo.toml
@@ -2,7 +2,7 @@
 name = "tvmasm"
 description = "CLI for TVM Assembler"
 repository = "https://github.com/broxus/everscale-asm"
-version = "0.0.4"
+version = "0.0.5"
 edition = "2021"
 rust-version = "1.70"
 include = ["src/**/*.rs", "src/**/*.tvm", "./LICENSE-*", "./README.md"]
@@ -24,4 +24,4 @@ tracing-subscriber = { version = "0.3", features = ["env-filter"] }
 unicode-width = "0.1"
 
 everscale-types = { version = "0.1.0-rc.6", default-features = false }
-everscale-asm = { path = "../", version = "0.0.3" }
+everscale-asm = { path = "../", version = "0.0.4" }
diff --git a/extension/package.json b/extension/package.json
@@ -4,7 +4,8 @@
   "description": "Language client extension for TVM Assembler",
   "publisher": "Rexagon",
   "license": "MIT",
-  "version": "0.0.2",
+  "homepage": "https://github.com/broxus/everscale-asm/blob/master/README.md",
+  "version": "0.0.3",
   "engines": {
     "vscode": "^1.65.0"
   },

diff --git a/extension/syntaxes/tvm.tmLanguage.json b/extension/syntaxes/tvm.tmLanguage.json
@@ -32,7 +32,7 @@
       "patterns": [
         {
           "name": "entity.name.function",
-          "match": "([0-9]?[A-Z#_][a-zA-Z0-9#_]*)"
+          "match": "(-?[0-9]?[A-Z#_][a-zA-Z0-9#_]*)"
         }
       ]
     },

diff --git a/src/asm/opcodes.rs b/src/asm/opcodes.rs
@@ -205,7 +205,7 @@ fn register_stackops(t: &mut Opcodes) {
         "XCPU" => 0x51(s, s),
         "PUXC" => 0x52(s, s, adj = 0x01),
         "PUSH2" => 0x53(s, s),
-        "XCHG3_l" => 0x540(s, s, s),
+        "XCHG3_L" => 0x540(s, s, s),
         "XC2PU" => 0x541(s, s, s),
         "XCPUXC" => 0x542(s, s, s, adj = 0x001),
         "XCPU2" => 0x543(s, s, s),
@@ -525,20 +525,20 @@ fn register_stackops(t: &mut Opcodes) {
         "STUXQ" => 0xcf05,
         "STIXRQ" => 0xcf06,
         "STUXRQ" => 0xcf07,
-        "STI_l" => 0xcf08(u8 - 1),
-        "STU_l" => 0xcf09(u8 - 1),
+        "STI_L" => 0xcf08(u8 - 1),
+        "STU_L" => 0xcf09(u8 - 1),
         "STIR" => 0xcf0a(u8 - 1),
         "STUR" => 0xcf0b(u8 - 1),
         "STIQ" => 0xcf0c(u8 - 1),
         "STUQ" => 0xcf0d(u8 - 1),
         "STIRQ" => 0xcf0e(u8 - 1),
         "STURQ" => 0xcf0f(u8 - 1),
-        "STREF_l" => 0xcf10,
+        "STREF_L" => 0xcf10,
         "STBREF" => 0xcf11,
-        "STSLICE_l" => 0xcf12,
+        "STSLICE_L" => 0xcf12,
         "STB" => 0xcf13,
         "STREFR" => 0xcf14,
-        "STBREFR_l" => 0xcf15,
+        "STBREFR_L" => 0xcf15,
         "STSLICER" => 0xcf16,
         "STBR" | "BCONCAT" => 0xcf17,
         "STREFQ" => 0xcf18,
@@ -594,8 +594,8 @@ fn register_stackops(t: &mut Opcodes) {
         "LDUXQ" => 0xd705,
         "PLDIXQ" => 0xd706,
         "PLDUXQ" => 0xd707,
-        "LDI_l" => 0xd708(u8 - 1),
-        "LDU_l" => 0xd709(u8 - 1),
+        "LDI_L" => 0xd708(u8 - 1),
+        "LDU_L" => 0xd709(u8 - 1),
         "PLDI" => 0xd70a(u8 - 1),
         "PLDU" => 0xd70b(u8 - 1),
         "LDIQ" => 0xd70c(u8 - 1),
@@ -607,7 +607,7 @@ fn register_stackops(t: &mut Opcodes) {
         "PLDSLICEX" => 0xd719,
         "LDSLICEXQ" => 0xd71a,
         "PLDSLICEXQ" => 0xd71b,
-        "LDSLICE_l" => 0xd71c(u8 - 1),
+        "LDSLICE_L" => 0xd71c(u8 - 1),
         "PLDSLICE" => 0xd71d(u8 - 1),
         "LDSLICEQ" => 0xd71e(u8 - 1),
         "PLDSLICEQ" => 0xd71f(u8 - 1),

diff --git a/src/ast.rs b/src/ast.rs
@@ -127,6 +127,14 @@ fn instr_ident<'a>() -> impl Parser<'a, &'a str, &'a str, extra::Err<ParserError
                     break 'char None;
                 };
 
+                if *first == '-' {
+                    chars.next();
+                }
+
+                let Some(first) = chars.peek() else {
+                    break 'char None;
+                };
+
                 if first.is_ascii_digit() {
                     chars.next();
                     let Some(second) = chars.next() else {