fixing a few layout bugs, fixing a windows compile bug

broccolimicro · Nov 13, 2024 · 7d1881a · 7d1881a
1 parent 1bc6315
commit 7d1881a
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Showing 3 changed files with 16 additions and 4 deletions.
diff --git a/bin/ckt b/bin/ckt
diff --git a/lib/phy b/lib/phy
diff --git a/tech/sky130/tech.py b/tech/sky130/tech.py
@@ -1,5 +1,3 @@
-#!/usr/bin/python3
-
 from loom import *
 
 AL = 0  # do not change
@@ -268,6 +266,8 @@
 nvtn = paint("nvtn", 251, 0)
 
 # Define DRC Rules
+difftap = b_or(diff, tap)
+
 fill(nwell)
 fill(nwell_pin)
 fill(nwell_label)
@@ -276,6 +276,7 @@
 fill(lvtn)
 fill(nsdm)
 fill(psdm)
+fill(hvi)
 fill(pwell_pin)
 fill(pwell_label)
 width(diff, 30)
@@ -343,6 +344,17 @@
 spacing(b_and(licon1, poly), b_or(diff, tap), 38)
 spacing(b_and(poly, b_not(diff)), diff, 15)
 
+width(hvi, 120)
+spacing(hvi, hvi, 140)
+#spacing(b_and(hvi, nwell), nwell, 400)
+#width(b_and(b_and(diff, hvi), b_not(b_and(psdm, diff))), 58)
+#width(b_and(b_and(diff, hvi), b_and(psdm, diff)), 30)
+enclosing(hvi, b_and(difftap, nwell), 66)
+spacing(b_and(hvi, nwell), difftap, 86)
+enclosing(hvi, difftap, 36)
+spacing(hvi, difftap, 36)
+#spacing(b_and(b_and(hvi, diff), b_not(nwell)), nwell, 86)
+
 bound(areaid_sc)
 
 # Define Routing and Device Models
+64 −39		phy/Layout.cpp
+2 −3		phy/Layout.h
+5 −0		phy/vector.h