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major rearch of technology file in support of PN ratio and extraction
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fix placer bug
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@nbingham1
nbingham1 committed Nov 21, 2024
1 parent 9faf7bd commit 104616d
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Showing 5 changed files with 58 additions and 43 deletions.
2 changes: 1 addition & 1 deletion lib/interpret_phy
Submodule interpret_phy updated 1 files
+4 −4 interpret_phy/export.cpp
2 changes: 1 addition & 1 deletion lib/phy
Submodule phy updated 5 files
+439 −148 phy/Layout.cpp
+34 −19 phy/Layout.h
+168 −100 phy/Script.cpp
+104 −43 phy/Tech.cpp
+82 −25 phy/Tech.h
2 changes: 1 addition & 1 deletion lib/prs
Submodule prs updated 1 files
+2 −2 prs/synthesize.cpp
2 changes: 1 addition & 1 deletion lib/sch
Submodule sch updated 7 files
+96 −187 sch/Draw.cpp
+1 −1 sch/Draw.h
+4 −7 sch/Placer.cpp
+24 −23 sch/Router.cpp
+2 −2 sch/Router.h
+7 −10 sch/Subckt.cpp
+15 −58 sch/Tapeout.cpp
93 changes: 54 additions & 39 deletions tech/sky130/tech.py
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Original file line number Diff line number Diff line change
Expand Up @@ -358,48 +358,63 @@
bound(areaid_sc)

# Define Routing and Device Models
df = subst(diff, diff_label, diff_pin)
ns = subst(nsdm, no, no)
ps = subst(psdm, no, no)
hvp = subst(hvtp, no, no)
hvn = subst(hvntm, no, no) # TODO(edward.bingham) DRC rules
lvn = subst(lvtn, no, no) # TODO(edward.bingham) DRC rules
nvn = subst(nvtn, no, no) # TODO(edward.bingham) DRC rules
hvx = subst(hvi, no, no) # TODO(edward.bingham) DRC rules
nw = well(nwell, nwell_label, nwell_pin)
pw = well(no, pwell_label, pwell_pin)
nw = well(nwell, nwell_label, nwell_pin, resist=1700)
pw = well(no, pwell_label, pwell_pin, resist=3050)

p = route(poly, poly_label, poly_pin)
m0 = route(li1, li1_label, li1_pin)
m1 = route(met1, met1_label, met1_pin)
m2 = route(met2, met2_label, met2_pin)
m3 = route(met3, met3_label, met3_pin)
m4 = route(met4, met4_label, met4_pin)
m5 = route(met5, met5_label, met5_pin)
nd = subst(diff, diff_label, diff_pin, mask=[nsdm], excl=[hvtp, lvtn, hvi], well=pw, thick=.12, resist=120)
nd_lvt = subst(diff, diff_label, diff_pin, mask=[nsdm, lvtn], excl=[nvtn], well=pw, thick=.12, resist=120)
nd_nvt = subst(diff, diff_label, diff_pin, mask=[nsdm, nvtn], well=pw, thick=.12, resist=120)
nd_pin = subst(diff, diff_label, diff_pin, mask=[nsdm, hvtp, hvi], well=pw, thick=.12, resist=120)

nfet = nmos("svt", "sky130_fd_pr__nfet_01v8", [df, ns, pw], exclude=[hvp, lvn, hvx], bins=[(0,500)])
nfet_lvt = nmos("lvt", "sky130_fd_pr__nfet_01v8_lvt", [df, ns, lvn, pw], exclude=[nvn], bins=[(0,500)])
nfet_pin = nmos("npin", "sky130_fd_pr__nfet_g5v0d10v5", [df, ns, hvn, pw, hvx])
nfet_nvt = nmos("nvt", "sky130_fd_pr__nfet_05v0_nvt", [df, ns, nvn, lvn, pw])
pd = subst(diff, diff_label, diff_pin, mask=[psdm], excl=[hvtp, lvtn, hvi], well=nw, thick=.12, resist=197)
pd_hvt = subst(diff, diff_label, diff_pin, mask=[psdm, hvtp], well=nw, thick=.12, resist=197)
pd_lvt = subst(diff, diff_label, diff_pin, mask=[psdm, lvtn], well=nw, thick=.12, resist=197)
pd_pin = subst(diff, diff_label, diff_pin, mask=[psdm, hvi], well=nw, thick=.12, resist=197)

pfet = pmos("svt", "sky130_fd_pr__pfet_01v8", [df, ps, nw], exclude=[hvp, lvn, hvx], bins=[(0,500)])
pfet_hvt = pmos("hvt", "sky130_fd_pr__pfet_01v8_hvt", [df, ps, hvp, nw], bins=[(0,500)])
pfet_lvt = pmos("lvt", "sky130_fd_pr__pfet_01v8_lvt", [df, ps, lvn, nw], bins=[(0,500)])
pfet_pin = pmos("ppin", "sky130_fd_pr__pfet_g5v0d10v5", [df, ps, nw, hvx])
p = route(poly, poly_label, poly_pin, thick=.18, resist=48.2)
m0 = route(li1, li1_label, li1_pin, thick=.1, resist=12.8)
m1 = route(met1, met1_label, met1_pin, thick=.36, resist=0.125)
m2 = route(met2, met2_label, met2_pin, thick=.36, resist=0.125)
m3 = route(met3, met3_label, met3_pin, thick=.845, resist=0.047)
m4 = route(met4, met4_label, met4_pin, thick=.845, resist=0.047)
m5 = route(met5, met5_label, met5_pin, thick=1.26, resist=0.029)

via(nfet, m0, licon1)
via(nfet_lvt, m0, licon1)
via(nfet_pin, m0, licon1)
via(nfet_nvt, m0, licon1)
via(pfet, m0, licon1)
via(pfet_hvt, m0, licon1)
via(pfet_lvt, m0, licon1)
via(pfet_pin, m0, licon1)
via(p, m0, licon1)
via(m0, m1, mcon)
via(m1, m2, via1)
via(m2, m3, via2)
via(m3, m4, via3)
via(m4, m5, via4)
via(nd, m0, licon1, thick=.9361, resist=185)
via(nd_lvt, m0, licon1, thick=.9361, resist=185)
via(nd_pin, m0, licon1, thick=.9361, resist=185)
via(nd_nvt, m0, licon1, thick=.9361, resist=185)
via(pd, m0, licon1, thick=.9361, resist=585)
via(pd_hvt, m0, licon1, thick=.9361, resist=585)
via(pd_lvt, m0, licon1, thick=.9361, resist=585)
via(pd_pin, m0, licon1, thick=.9361, resist=585)
via(p, m0, licon1, thick=.4299, resist=150)
via(m0, m1, mcon, thick=.365, resist=152)
via(m1, m2, via1, thick=.27, resist=4.5)
via(m2, m3, via2, thick=.42, resist=3.41)
via(m3, m4, via3, thick=.39, resist=3.41)
via(m4, m5, via4, thick=.505, resist=.380)

dielec(nd, p, thick=.3262, permit=34.6193)
dielec(nd_lvt, p, thick=.3262, permit=34.6193)
dielec(nd_nvt, p, thick=.3262, permit=34.6193)
dielec(nd_pin, p, thick=.3262, permit=34.6193)
dielec(pd, p, thick=.3262, permit=34.6193)
dielec(pd_hvt, p, thick=.3262, permit=34.6193)
dielec(pd_lvt, p, thick=.3262, permit=34.6193)
dielec(pd_pin, p, thick=.3262, permit=34.6193)
dielec(p, m0, thick=0.4299, permit=40.48127556)
dielec(m0, m1, thick=0.365, permit=41.681905)
dielec(m1, m2, thick=0.27, permit=36.14247)
dielec(m2, m3, thick=0.42, permit=36.198162)
dielec(m3, m4, thick=0.39, permit=32.773494)
dielec(m4, m5, thick=0.505, permit=34.504226)

nmos("svt", "sky130_fd_pr__nfet_01v8", nd, bins=[(0,500)])
nmos("lvt", "sky130_fd_pr__nfet_01v8_lvt", nd_lvt, bins=[(0,500)])
nmos("nvt", "sky130_fd_pr__nfet_05v0_nvt", nd_nvt)
nmos("npin", "sky130_fd_pr__nfet_g5v0d10v5", nd_pin)

pmos("svt", "sky130_fd_pr__pfet_01v8", pd, bins=[(0,500)])
pmos("hvt", "sky130_fd_pr__pfet_01v8_hvt", pd_hvt, bins=[(0,500)])
pmos("lvt", "sky130_fd_pr__pfet_01v8_lvt", pd_lvt, bins=[(0,500)])
pmos("ppin", "sky130_fd_pr__pfet_g5v0d10v5", pd_pin)

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