Design of a digital clock in Xilinx ISE.
This project was the final project of my 2nd year Electrical Engineering course Digital Systems(EE243).
In this project I designed all the components of a digital clock starting from the gate level. (Such as NAND, AND, OR, NOT).
Achieving this required a well-established understanding of combinatinal and sequential circuits as well as proefficiency in working with latches, flip-flops and registers.
For this clock to work in real time it should be fed with an external 1 Hz clock throught the 'clock' input.
In order to see the full design extract the zip folder and open it in Xilinx ISE 14.7 Schematic Editor.
You can also see the pre-prepared simulations and sythesize your own vhd code to try it for yourself.