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Connections Monochrome

board707 edited this page May 11, 2024 · 4 revisions

Connections - Monochrome

Using of SPI bus - DMD_MonoChrome_SPI.h

(R)DATA CLK SCLK pins are used to load data into the DMD module. It correspond to the DATA, CLOCK and LATCH inputs of shift register, since the operation of the DMD is also based on shift registers. In this mode, the SPI bus is used for data transfer, which limits the choose of pins for the DATA and CLK lines to the MOSI and SCK pins of the corresponding SPI bus. On STM32F103 boards it will be A7 A5 in the case of SPI (1) or PB15 PB13 for SPI (2), respectively. Pin SCLK can be connected to any free digital pin of the controller.

Even though SPI receiving is not used, you should not connect anything to the MISO pin of the SPI channel you are using.

OE (Output Enable) – used to turn the LEDs on and off. By applying a PWM signal to this input, you can control the brightness of the panels. By default, the library uses the TIM3 timer to generate PWM, so for OE should be selected one of the timer outputs - pins (PB0 or PB1), as well as A6 A7 if the SPI (1) channel is not enabled.

A B – switches. Only a quarter of the panel is powered at any one time. Quickly switching between parts, get the effect of the full image. Level combinations on pins A B allow to select which of the 4 parts is currently highlighted. For these pins, you can use any GPIOs.

GND just connect one, they are all connected on the panel. Pins marked NC are not used and may not be connected anywhere.

If the cable between the controller and the first panel is longer than 20-30cm, it is recommended to use a logic level converter between 3.3v and 5v.

Limitations - I'm not entirely sure, but the following pins are not recommended: PB3/PB4 (JTAG), PA11/PA12 (USB D+ D-)

Connecting more than one panel

Each panel has two connectors, usually marked as INPUT and OUTPUT, which allows you to connect panels in chains. Physically the panels can only connect linearly, but logically the controller can be told to treat a chain of 6 panels as a 3x2 rectangular matrix. To do this, use the macros at the beginning of the code:

#define DISPLAYS_ACROSS 3    // number of panels in X axis
#define DISPLAYS_DOWN 2      // and Y axis

The connection between panels in a rectangular matrix can be made in different ways. Since v0.6 the library supports two options: CONNECT_NORMAL and CONNECT_ZIGZAG. By default, the NORMAL scheme is used, in this mode the output to the display is the fastest.

The ZIGZAG scheme allows you to use shorter cables, but requires additional image transformation and is not recommended for dynamic applications. Also, be aware that in this mode every second row of panels should be rotated upside down by 180 degrees, which is not suitable for panels with covers above the LEDs.

To select the panel connection scheme, use the instruction:

dmd.setConnectScheme(CONNECT_ZIGZAG);

Parrallel connection - DMD_Monochrome_Parallel.h

This mode is intended for large rectangular screens with many rows of panels. In this mode, the DATA input of each horizontal row of panels is connected to separate controller output. Every other lines are joined for all rows. Data outputs to all rows simultaneously (in parallel) by direct writing to the port. This gives a speed advantage if your matrix contains many horizontal rows, but requires more RAM. The A B OE SCLK pins are selected in the same way as for the DMD_MonoChrome_SPI.h module. The common pin CLK and separate pins DATA for each row are specified as a list, the first pin is CLK, then the pins DATA from the top row to the bottom:

// all those pins must be selected from lower byte of same port!
uint8_t pins[] = { PA5, PA7, PA6 };  // CLK , row1, row 2

//Fire up the DMD object as dmd
DMD_Monochrome_Parallel dmd(DMD_PIN_A, DMD_PIN_B, DMD_PIN_nOE, DMD_PIN_SCLK, pins, DISPLAYS_ACROSS, DISPLAYS_DOWN,ENABLE_DUAL_BUFFER);

Note! All those pins must be selected from lower byte of same port! so it should be selected from the ranges A0-A7 or B0-B7. Thus, the maximum number of horizontal rows with this scheme is 7. ZIGZAG mode is not supported

Since version v0.7.0, it became possible to select the lower or upper byte of the port for the CLK and DATA signals. However, note that all the pins of the list must still be located in the same byte. To select pins in the upper half of the port, uncomment the USE_UPPER_8BIT setting in DMD_Config.h.

See also: Connection - RGB panels