Second Round of ISA Agnostic Changes

machines/Makefile

@@ -3,6 +3,7 @@
 BSG_MANYCORE_DIR := $(shell git rev-parse --show-toplevel)
 # By convention, basejump_stl is in the same directory as $(BSG_MANYCORE_DIR)
 BASEJUMP_STL_DIR := $(abspath $(BSG_MANYCORE_DIR)/../basejump_stl)
+BSG_MANYCORE_ISA_DIR := $(abspath $(BSG_MANYCORE_DIR)/../bsg_manycore_ISA)
 
 ifeq ($(wildcard $(BASEJUMP_STL_DIR)/imports/DRAMSim3/Makefile),)
 $(error DRAMSim3 has not been submoduled in basejump_stl, see top-level README.md)
@@ -20,8 +21,19 @@ DEFAULT_PROFILE_TARGETS = $(foreach machine, $(DEFAULT_MACHINES),$(machine)/$(BS
 all: $(DEFAULT_TARGETS) $(DEFAULT_DEBUG_TARGETS) $(DEFAULT_PROFILE_TARGETS)
 
 # Include source lists
-include arch_filelist.mk
-include sim_filelist.mk
+# We include different source lists for different ISAs
+ifeq ($(BSG_MACHINE_ISA),VANILLA)
+include $(BSG_MANYCORE_DIR)/machines/arch_filelist.mk
+else ifeq ($(BSG_MACHINE_ISA),RISCV)
+include $(BSG_MANYCORE_ISA_DIR)/RISCV/arch_filelist.mk
+endif
+
+# We include different sim lists for different ISAs
+ifeq ($(BSG_MACHINE_ISA),VANILLA)
+include $(BSG_MANYCORE_DIR)/machines/sim_filelist.mk
+else ifeq ($(BSG_MACHINE_ISA),RISCV)
+include $(BSG_MANYCORE_ISA_DIR)/RISCV/sim_filelist.mk
+endif
 
 include Makefile.vcs
 include Makefile.verilator

machines/platform.mk

@@ -1,5 +1,10 @@
 
 BSG_PLATFORM ?= vcs
+# Default Machine ISA is Vanilla. This can be modified to any of the supported ISA in the repository bsg_manycore_ISA
+# Note that you would have to sync the above repository as well to use another ISA
+# You can change the below to modify the machine built
+# BSG_MACHINE_ISA ?= VANILLA
+BSG_MACHINE_ISA ?= RISCV
 
 ifeq ($(BSG_PLATFORM),vcs)
 DEFAULT_MACHINES = pod_1x1 pod_1x1_hbm2 pod_4x4 pod_4x4_hbm2

testbenches/common/v/bsg_nonsynth_manycore_vanilla_core_pc_cov.sv

@@ -16,7 +16,7 @@ module bsg_nonsynth_manycore_vanilla_core_pc_cov
   ,input reset_down
 
   // Instruction
-  ,input instruction_s instruction
+  ,input instruction_s instruction_r
 
   // Pipeline registers
   ,input id_signals_s  id_r
@@ -47,7 +47,7 @@ module bsg_nonsynth_manycore_vanilla_core_pc_cov
   ,input coverage_en_i
   );
 
-  wire take_br = decode.is_branch_op & instruction[0];
+  wire take_br = decode.is_branch_op & instruction_r[0];
   wire take_jalr = decode.is_jal_op | decode.is_jalr_op;
 
   covergroup cg_pc_reset @(negedge clk_i);
@@ -131,7 +131,7 @@ module bsg_nonsynth_manycore_vanilla_core_pc_cov
   covergroup cg_pc_take_jump @(negedge clk_i iff ~reset_down);
 
     br_op: coverpoint decode.is_branch_op;
-    instr0: coverpoint instruction[0];
+    instr0: coverpoint instruction_r[0];
     jal_op: coverpoint decode.is_jal_op;
     jalr_op: coverpoint decode.is_jalr_op;
 

testbenches/common/v/nb_waw_detector.sv

@@ -4,8 +4,8 @@ module nb_waw_detector
     , parameter x_cord_width_p="inv"
     , parameter y_cord_width_p="inv"
 
-    , parameter reg_els_lp=RV32_reg_els_gp
-    , parameter instr_width_lp=RV32_instr_width_gp
+    , parameter reg_els_lp=reg_els_gp
+    , parameter instr_width_lp=instr_width_gp
   )
   (
     input clk_i
@@ -18,7 +18,7 @@ module nb_waw_detector
 
     , input int_remote_load_resp_v_i
     , input int_remote_load_resp_force_i
-    , input [RV32_reg_addr_width_gp-1:0] int_remote_load_resp_rd_i
+    , input [reg_addr_width_gp-1:0] int_remote_load_resp_rd_i
 
     , input mem_signals_s mem_r
     , input wb_signals_s wb_r

testbenches/common/v/remote_load_trace.sv

@@ -55,7 +55,7 @@ module remote_load_trace
 
     // Load response coming back
     , input returned_v_i
-    , input [RV32_reg_addr_width_gp-1:0] returned_reg_id_i
+    , input [reg_addr_width_gp-1:0] returned_reg_id_i
     , input bsg_manycore_return_packet_type_e returned_pkt_type_i
     , input returned_yumi_o
 
@@ -95,8 +95,8 @@ module remote_load_trace
   } remote_load_status_s;
 
 
-  remote_load_status_s [RV32_reg_els_gp-1:0] int_rl_status_r;
-  remote_load_status_s [RV32_reg_els_gp-1:0] float_rl_status_r;
+  remote_load_status_s [reg_els_gp-1:0] int_rl_status_r;
+  remote_load_status_s [reg_els_gp-1:0] float_rl_status_r;
   remote_load_status_s icache_status_r;
 
   wire int_rl_v    = out_v_o & (
@@ -112,19 +112,19 @@ module remote_load_trace
   wire icache_rl_v = out_v_o & (
     (out_packet.op_v2 == e_remote_load) & load_info.icache_fetch);
 
-  logic [RV32_reg_els_gp-1:0] int_rl_we;
-  logic [RV32_reg_els_gp-1:0] float_rl_we;
+  logic [reg_els_gp-1:0] int_rl_we;
+  logic [reg_els_gp-1:0] float_rl_we;
 
   bsg_decode_with_v #(
-    .num_out_p(RV32_reg_els_gp)
+    .num_out_p(reg_els_gp)
   ) dv0 (
     .i(out_packet.reg_id)
     ,.v_i(int_rl_v)
     ,.o(int_rl_we)
   );
 
   bsg_decode_with_v #(
-    .num_out_p(RV32_reg_els_gp)
+    .num_out_p(reg_els_gp)
   ) dv1 (
     .i(out_packet.reg_id)
     ,.v_i(float_rl_v)
@@ -148,7 +148,7 @@ module remote_load_trace
     end
     else begin
 
-      for (integer i = 0 ; i < RV32_reg_els_gp; i++) begin
+      for (integer i = 0 ; i < reg_els_gp; i++) begin
         if (int_rl_we[i])
           int_rl_status_r[i] <= next_rl;
         if (float_rl_we[i])

testbenches/common/v/vanilla_core_pc_histogram.sv

@@ -15,8 +15,8 @@ module vanilla_core_pc_histogram
     ,parameter `BSG_INV_PARAM(origin_y_cord_p)
     ,parameter icache_addr_width_lp=`BSG_SAFE_CLOG2(icache_entries_p)
     ,parameter pc_width_lp=(icache_tag_width_p+icache_addr_width_lp)
-    ,parameter reg_els_lp=RV32_reg_els_gp
-    ,parameter reg_addr_width_lp=RV32_reg_addr_width_gp
+    ,parameter reg_els_lp=reg_els_gp
+    ,parameter reg_addr_width_lp=reg_addr_width_gp
     )
   (
    input clk_i
@@ -28,7 +28,7 @@ module vanilla_core_pc_histogram
    , input [data_width_p-1:0] if_pc
    , input [data_width_p-1:0] id_pc
    , input [data_width_p-1:0] exe_pc
-   , input instruction_s instruction
+   , input instruction_s instruction_r
    , input decode_s decode
 
    , input flush
@@ -61,7 +61,7 @@ module vanilla_core_pc_histogram
    , input jalr_mispredict
 
    , input [data_width_p-1:0] rs1_val_to_exe
-   , input [RV32_Iimm_width_gp-1:0] mem_addr_op2
+   , input [Iimm_width_gp-1:0] mem_addr_op2
 
    , input int_sb_clear
    , input float_sb_clear

testbenches/common/v/vanilla_core_profiler.sv

@@ -1,5 +1,5 @@
 /**
- *    vanilla_core_profiler.v
+ *    vanilla_core_profiler.sv
  *
  */
 
@@ -32,8 +32,8 @@ module vanilla_core_profiler
     , parameter icache_addr_width_lp=`BSG_SAFE_CLOG2(icache_entries_p)
     , parameter pc_width_lp=(icache_tag_width_p+icache_addr_width_lp)
 
-    , parameter reg_els_lp = RV32_reg_els_gp
-    , parameter reg_addr_width_lp = RV32_reg_addr_width_gp
+    , parameter reg_els_lp = reg_els_gp
+    , parameter reg_addr_width_lp = reg_addr_width_gp
 
     , parameter period_p = 250
     , parameter enable_periodic_p=0
@@ -82,7 +82,7 @@ module vanilla_core_profiler
     , input remote_req_s remote_req_o
 
     , input [data_width_p-1:0] rs1_val_to_exe
-    , input [RV32_Iimm_width_gp-1:0] mem_addr_op2
+    , input [Iimm_width_gp-1:0] mem_addr_op2
 
     , input int_sb_clear
     , input float_sb_clear
@@ -94,7 +94,7 @@ module vanilla_core_profiler
     , input fp_exe_ctrl_signals_s fp_exe_ctrl_r
 
     // IF stage
-    , input instruction_s instruction
+    , input instruction_s instruction_r
     , input decode_s decode
 
     , input [x_cord_width_p-1:0] global_x_i
@@ -207,12 +207,12 @@ module vanilla_core_profiler
   wire amoadd_inc = exe_r.decode.is_amo_op & (exe_r.decode.amo_type == e_vanilla_amoadd);
 
   // branch & jump
-  wire beq_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `RV32_BEQ);
-  wire bne_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `RV32_BNE);
-  wire blt_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `RV32_BLT);
-  wire bge_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `RV32_BGE);
-  wire bltu_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `RV32_BLTU);
-  wire bgeu_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `RV32_BGEU);
+  wire beq_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `VANILLA_BEQ);
+  wire bne_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `VANILLA_BNE);
+  wire blt_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `VANILLA_BLT);
+  wire bge_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `VANILLA_BGE);
+  wire bltu_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `VANILLA_BLTU);
+  wire bgeu_inc = exe_r.decode.is_branch_op & (exe_r.instruction ==? `VANILLA_BGEU);
 
   wire jal_inc = exe_r.decode.is_jal_op;
   wire jalr_inc = exe_r.decode.is_jalr_op;
@@ -227,29 +227,29 @@ module vanilla_core_profiler
   wire jalr_miss_inc = jalr_inc & jalr_mispredict;
 
   // ALU
-  wire sll_inc = (exe_r.instruction ==? `RV32_SLL);
-  wire slli_inc = (exe_r.instruction ==? `RV32_SLLI);
-  wire srl_inc = (exe_r.instruction ==? `RV32_SRL);
-  wire srli_inc = (exe_r.instruction ==? `RV32_SRLI);
-  wire sra_inc = (exe_r.instruction ==? `RV32_SRA);
-  wire srai_inc = (exe_r.instruction ==? `RV32_SRAI);
-
-  wire add_inc = (exe_r.instruction ==? `RV32_ADD);
-  wire addi_inc = (exe_r.instruction ==? `RV32_ADDI);
-  wire sub_inc = (exe_r.instruction ==? `RV32_SUB);
-  wire lui_inc = (exe_r.instruction ==? `RV32_LUI);
-  wire auipc_inc = (exe_r.instruction ==? `RV32_AUIPC);
-  wire xor_inc = (exe_r.instruction ==? `RV32_XOR);
-  wire xori_inc = (exe_r.instruction ==? `RV32_XORI);
-  wire or_inc = (exe_r.instruction ==? `RV32_OR);
-  wire ori_inc = (exe_r.instruction ==? `RV32_ORI);
-  wire and_inc = (exe_r.instruction ==? `RV32_AND);
-  wire andi_inc = (exe_r.instruction ==? `RV32_ANDI);
-
-  wire slt_inc = (exe_r.instruction ==? `RV32_SLT);
-  wire slti_inc = (exe_r.instruction ==? `RV32_SLTI);
-  wire sltu_inc = (exe_r.instruction ==? `RV32_SLTU);
-  wire sltiu_inc = (exe_r.instruction ==? `RV32_SLTIU);
+  wire sll_inc = (exe_r.instruction ==? `VANILLA_SLL);
+  wire slli_inc = (exe_r.instruction ==? `VANILLA_SLLI);
+  wire srl_inc = (exe_r.instruction ==? `VANILLA_SRL);
+  wire srli_inc = (exe_r.instruction ==? `VANILLA_SRLI);
+  wire sra_inc = (exe_r.instruction ==? `VANILLA_SRA);
+  wire srai_inc = (exe_r.instruction ==? `VANILLA_SRAI);
+
+  wire add_inc = (exe_r.instruction ==? `VANILLA_ADD);
+  wire addi_inc = (exe_r.instruction ==? `VANILLA_ADDI);
+  wire sub_inc = (exe_r.instruction ==? `VANILLA_SUB);
+  wire lui_inc = (exe_r.instruction ==? `VANILLA_LUI);
+  wire auipc_inc = (exe_r.instruction ==? `VANILLA_AUIPC);
+  wire xor_inc = (exe_r.instruction ==? `VANILLA_XOR);
+  wire xori_inc = (exe_r.instruction ==? `VANILLA_XORI);
+  wire or_inc = (exe_r.instruction ==? `VANILLA_OR);
+  wire ori_inc = (exe_r.instruction ==? `VANILLA_ORI);
+  wire and_inc = (exe_r.instruction ==? `VANILLA_AND);
+  wire andi_inc = (exe_r.instruction ==? `VANILLA_ANDI);
+
+  wire slt_inc = (exe_r.instruction ==? `VANILLA_SLT);
+  wire slti_inc = (exe_r.instruction ==? `VANILLA_SLTI);
+  wire sltu_inc = (exe_r.instruction ==? `VANILLA_SLTU);
+  wire sltiu_inc = (exe_r.instruction ==? `VANILLA_SLTIU);
 
   // IDIV
   wire div_inc = exe_r.decode.is_idiv_op & (exe_r.decode.idiv_op == eDIV);
@@ -264,16 +264,16 @@ module vanilla_core_profiler
   wire fence_inc = exe_r.decode.is_fence_op;
 
   // CSR
-  wire csrrw_inc = (exe_r.instruction ==? `RV32_CSRRW);
-  wire csrrs_inc = (exe_r.instruction ==? `RV32_CSRRS);
-  wire csrrc_inc = (exe_r.instruction ==? `RV32_CSRRC);
-  wire csrrwi_inc = (exe_r.instruction ==? `RV32_CSRRWI);
-  wire csrrsi_inc = (exe_r.instruction ==? `RV32_CSRRSI);
-  wire csrrci_inc = (exe_r.instruction ==? `RV32_CSRRCI);
+  wire csrrw_inc = (exe_r.instruction ==? `VANILLA_CSRRW);
+  wire csrrs_inc = (exe_r.instruction ==? `VANILLA_CSRRS);
+  wire csrrc_inc = (exe_r.instruction ==? `VANILLA_CSRRC);
+  wire csrrwi_inc = (exe_r.instruction ==? `VANILLA_CSRRWI);
+  wire csrrsi_inc = (exe_r.instruction ==? `VANILLA_CSRRSI);
+  wire csrrci_inc = (exe_r.instruction ==? `VANILLA_CSRRCI);
 
   // Barrier Instruction
-  wire barsend_inc = (exe_r.instruction ==? `RV32_FENCE_OP) & (exe_r.instruction[31:28] == `RV32_BARSEND_FM);
-  wire barrecv_inc = (exe_r.instruction ==? `RV32_FENCE_OP) & (exe_r.instruction[31:28] == `RV32_BARRECV_FM);
+  wire barsend_inc = (exe_r.instruction ==? `VANILLA_FENCE_OP) & (exe_r.instruction[31:28] == `VANILLA_BARSEND_FM);
+  wire barrecv_inc = (exe_r.instruction ==? `VANILLA_FENCE_OP) & (exe_r.instruction[31:28] == `VANILLA_BARRECV_FM);
 
   // Track bubbles in the EXE stage
   // and their associated PC

testbenches/common/v/vanilla_core_trace.sv

@@ -13,7 +13,7 @@ module vanilla_core_trace
     , localparam icache_addr_width_lp=`BSG_SAFE_CLOG2(icache_entries_p)
     , localparam dmem_addr_width_lp=`BSG_SAFE_CLOG2(dmem_size_p)
     , localparam pc_width_lp=(icache_tag_width_p+icache_addr_width_lp)
-    , localparam reg_addr_width_lp=RV32_reg_addr_width_gp
+    , localparam reg_addr_width_lp=reg_addr_width_gp
 
   )
   (
@@ -56,52 +56,52 @@ module vanilla_core_trace
 
   typedef struct packed
   {
-    logic [RV32_reg_data_width_gp-1:0] pc;
-    logic [RV32_instr_width_gp-1:0] instr;
+    logic [reg_data_width_gp-1:0] pc;
+    logic [instr_width_gp-1:0] instr;
     logic branch_or_jump;
-    logic [RV32_instr_width_gp-1:0] btarget;
+    logic [instr_width_gp-1:0] btarget;
     logic is_local_load;
     logic is_local_store;
     logic [dmem_addr_width_lp-1:0] local_dmem_addr;
-    logic [RV32_reg_data_width_gp-1:0] local_store_data;
+    logic [reg_data_width_gp-1:0] local_store_data;
     logic is_remote_load;
     logic is_remote_store;
-    logic [RV32_reg_data_width_gp-1:0] remote_addr;
-    logic [RV32_reg_data_width_gp-1:0] remote_store_data;
+    logic [reg_data_width_gp-1:0] remote_addr;
+    logic [reg_data_width_gp-1:0] remote_store_data;
   } exe_debug_s;
 
 
   typedef struct packed
   {
-    logic [RV32_reg_data_width_gp-1:0] pc;
-    logic [RV32_instr_width_gp-1:0] instr;
+    logic [reg_data_width_gp-1:0] pc;
+    logic [instr_width_gp-1:0] instr;
     logic branch_or_jump;
-    logic [RV32_instr_width_gp-1:0] btarget;
+    logic [instr_width_gp-1:0] btarget;
     logic is_local_load;
     logic is_local_store;
     logic [dmem_addr_width_lp-1:0] local_dmem_addr;
-    logic [RV32_reg_data_width_gp-1:0] local_store_data;
+    logic [reg_data_width_gp-1:0] local_store_data;
     logic is_remote_load;
     logic is_remote_store;
-    logic [RV32_reg_data_width_gp-1:0] remote_addr;
-    logic [RV32_reg_data_width_gp-1:0] remote_store_data;
+    logic [reg_data_width_gp-1:0] remote_addr;
+    logic [reg_data_width_gp-1:0] remote_store_data;
   } mem_debug_s;
 
   typedef struct packed
   {
-    logic [RV32_reg_data_width_gp-1:0] pc;
-    logic [RV32_instr_width_gp-1:0] instr;
+    logic [reg_data_width_gp-1:0] pc;
+    logic [instr_width_gp-1:0] instr;
     logic branch_or_jump;
-    logic [RV32_instr_width_gp-1:0] btarget;
+    logic [instr_width_gp-1:0] btarget;
     logic is_local_load;
     logic is_local_store;
     logic [dmem_addr_width_lp-1:0] local_dmem_addr;
-    logic [RV32_reg_data_width_gp-1:0] local_load_data;
-    logic [RV32_reg_data_width_gp-1:0] local_store_data;
+    logic [reg_data_width_gp-1:0] local_load_data;
+    logic [reg_data_width_gp-1:0] local_store_data;
     logic is_remote_load;
     logic is_remote_store;
-    logic [RV32_reg_data_width_gp-1:0] remote_addr;
-    logic [RV32_reg_data_width_gp-1:0] remote_store_data;
+    logic [reg_data_width_gp-1:0] remote_addr;
+    logic [reg_data_width_gp-1:0] remote_store_data;
   } wb_debug_s;
 
   exe_debug_s exe_debug;