Bigblade memory plumbing (#488)

* removing concentrator for test_mem

* remove concentrator hbm2 1x1

* num_vcache_rows_p test_mem

* num_vcache_rows_p hbm2

* num_vcaches_per_channel_p

* generalize mapping function

* add comment

* memtest2020 iterates twice

* machine variable README; VCACHE_BLOCK_SIZE macro

* dramsim3 blood graph

* rename

* move comment

* change num_pods to num_finish for more flexibility

* add ?

* prefetch bandwidth

* remove hard-code; swap ba, bg

* machine param change; bg target

* write bandwidth test

* dramsim3 pkg machine parameter

* add comment about cache-dramsim3 addr mapping

* add readme comment about BSG_MACHINE_DRAMSIM3_PKG

* revert default machine path; clean dramsim3 outputs

* reduce barrier time iteration time

* 4x4; fix dma to dram mapping

machines/.gitignore

@@ -5,9 +5,11 @@ simv-profile.daidir
 simv-debug
 vc_hdrs.h
 stack.info.*
+*/build-profile
 */build-debug
 */build
 */csrc
 */csrc-debug
+*/csrc-profile
 */*.tr
 */bsg_tag_boot_rom.v

machines/Makefile

@@ -72,6 +72,9 @@ define set_machine_variables
 	$(eval VCS_DEFINES += +define+BSG_MACHINE_RUCHE_FACTOR_X="${BSG_MACHINE_RUCHE_FACTOR_X}")
 	$(eval VCS_DEFINES += +define+BSG_MACHINE_SUBARRAY_X="${BSG_MACHINE_SUBARRAY_X}")
 	$(eval VCS_DEFINES += +define+BSG_MACHINE_SUBARRAY_Y="${BSG_MACHINE_SUBARRAY_Y}")
+	$(eval VCS_DEFINES += +define+BSG_MACHINE_NUM_VCACHE_ROWS="${BSG_MACHINE_NUM_VCACHE_ROWS}")
+	$(eval VCS_DEFINES += +define+BSG_MACHINE_NUM_VCACHES_PER_CHANNEL="${BSG_MACHINE_NUM_VCACHES_PER_CHANNEL}")
+	$(eval VCS_DEFINES += +define+BSG_MACHINE_DRAMSIM3_PKG="${BSG_MACHINE_DRAMSIM3_PKG}")
 	# specify where the host module is instantiated for profiler trigger (print_stat).
 	# relative to $root
 	$(eval VCS_DEFINES += +define+HOST_MODULE_PATH=spmd_testbench) 
@@ -114,9 +117,10 @@ ASCII_TO_ROM_PY = $(BASEJUMP_STL_DIR)/bsg_mem/bsg_ascii_to_rom.py
 	python $(POD_TRACE_GEN_PY) $(BSG_MACHINE_PODS_X) $(BSG_MACHINE_PODS_Y) > $*/pod_trace.tr
 	python $(ASCII_TO_ROM_PY) $*/pod_trace.tr bsg_tag_boot_rom > $*/bsg_tag_boot_rom.v
 	$(eval VCS_FLAGS += +define+BSG_ENABLE_PROFILING) # Debug adds these two variables to generate waveforms
+	$(eval VCS_CFLAGS   += -CFLAGS "-DBLOOD_GRAPH")
 	$(VCS) $(VCS_FLAGS) $(VCS_CFLAGS) -o $@ \
 		$(VCS_INCLUDES) $(VCS_DEFINES) $(CSOURCES) $(VCS_SOURCES) $*/bsg_tag_boot_rom.v \
-		-l $*/build.log -Mdir=$*/csrc
+		-l $*/build-profile.log -Mdir=$*/csrc-profile
 
 
 clean:

machines/README.md

@@ -3,10 +3,17 @@ Machine.machine.include parameters
 
 - BSG_MACHINE_GLOBAL_X                  =   x-dimension of manycore array.
 - BSG_MACHINE_GLOBAL_Y                  =   y-dimension of manycore array (including the io router row).
+
+- BSG_MACHINE_NUM_VCACHE_ROWS           =   number of vcache rows on each side of pod (north and south).
+                                            (allowed val = 1,2,4)
 - BSG_MACHINE_VCACHE_SET                =   number of sets in each vcache
 - BSG_MACHINE_VCACHE_WAY                =   number of ways in each vcache
 - BSG_MACHINE_VCACHE_BLOCK_SIZE_WORDS   =   number of words in each vcache block.
 - BSG_MACHINE_VCACHE_DMA_DATA_WIDTH     =   vcache dma interface data width.
+                                            (constraint: 32 <= DMA_DATA_WIDTH <= BLOCK_SIZE*32)
+- BSG_MACHINE_NUM_VCACHES_PER_CHANNEL   =   number of vcaches allocated per one HBM2 channel (only for e_vcache_hbm2)
+                                            (constraint for single pod: NUM_VCACHES_PER_CHANNEL <= 2*NUM_VCACHE_ROWS*BSG_MACHINE_GLOBAL_X)
+
 - BSG_MACHINE_VCACHE_MISS_FIFO_ELS      =   number of entries in miss fifo (non-blocking vcache only).
 - BSG_MACHINE_DRAM_SIZE_WORDS           =   the total size of main memory. 2GB max, but it can be set to lower.
 - BSG_MACHINE_DRAM_BANK_SIZE_WORDS      =   the size of address space spanned by each bank.
@@ -16,6 +23,7 @@ Machine.machine.include parameters
                                             meaning that the vcache is only used as block memory.
 - BSG_MACHINE_MAX_EPA_WIDTH             =   Width of word address on the mesh network.
 - BSG_MACHINE_MEM_CFG                   =   e_vcache_non_blocking_axi4_nonsynth_mem
+- BSG_MACHINE_DRAMSIM3_PKG              =   Specify the dramsim3 setting. (only applicable if BSG_MACHINE_MEM_CFG is hbm2)
 - BSG_MACHINE_BRANCH_TRACE_EN           =   Enable branch trace.
 - BSG_MACHINE_HETERO_TYPE_VEC           =   Hetero type vector. Default configuration is 'default:0'.
                                             Use this to instantiate custom accelerator instead of vanilla core.

machines/arch_filelist.mk

@@ -170,7 +170,6 @@ VSOURCES += $(BSG_MANYCORE_DIR)/v/vanilla_bean/regfile.v
 VSOURCES += $(BSG_MANYCORE_DIR)/v/vanilla_bean/regfile_synth.v
 VSOURCES += $(BSG_MANYCORE_DIR)/v/vanilla_bean/regfile_hard.v
 VSOURCES += $(BSG_MANYCORE_DIR)/v/vanilla_bean/scoreboard.v
-VSOURCES += $(BSG_MANYCORE_DIR)/v/vanilla_bean/hash_function.v
 
 VSOURCES += $(BSG_MANYCORE_DIR)/v/bsg_manycore_pod_ruche_array.v
 VSOURCES += $(BSG_MANYCORE_DIR)/v/bsg_manycore_pod_ruche.v

machines/pod_1x1/Makefile.machine.include

@@ -9,10 +9,13 @@ BSG_MACHINE_Y_CORD_WIDTH              = 7
 
 BSG_MACHINE_RUCHE_FACTOR_X            = 3
 
+BSG_MACHINE_NUM_VCACHE_ROWS           = 1
 BSG_MACHINE_VCACHE_SET                = 64
 BSG_MACHINE_VCACHE_WAY                = 4
 BSG_MACHINE_VCACHE_BLOCK_SIZE_WORDS   = 8
 BSG_MACHINE_VCACHE_DMA_DATA_WIDTH     = 32
+BSG_MACHINE_NUM_VCACHES_PER_CHANNEL   = 16
+
 
 BSG_MACHINE_DRAM_SIZE_WORDS           = 536870912
 BSG_MACHINE_DRAM_BANK_SIZE_WORDS      = 16777216
@@ -29,6 +32,7 @@ BSG_MACHINE_HOST_Y_CORD               = 0
 BSG_MACHINE_HOST_X_CORD               = 16
 
 BSG_MACHINE_MEM_CFG                   = e_vcache_test_mem
+BSG_MACHINE_DRAMSIM3_PKG              = bsg_dramsim3_hbm2_8gb_x128_pkg
 
 BSG_MACHINE_SUBARRAY_X                = 1
 BSG_MACHINE_SUBARRAY_Y                = 1

machines/pod_1x1_hbm2/Makefile.machine.include

@@ -9,10 +9,12 @@ BSG_MACHINE_Y_CORD_WIDTH              = 7
 
 BSG_MACHINE_RUCHE_FACTOR_X            = 3
 
-BSG_MACHINE_VCACHE_SET                = 64
+BSG_MACHINE_NUM_VCACHE_ROWS           = 2
 BSG_MACHINE_VCACHE_WAY                = 4
-BSG_MACHINE_VCACHE_BLOCK_SIZE_WORDS   = 8
-BSG_MACHINE_VCACHE_DMA_DATA_WIDTH     = 32
+BSG_MACHINE_VCACHE_SET                = 64
+BSG_MACHINE_VCACHE_BLOCK_SIZE_WORDS   = 16
+BSG_MACHINE_VCACHE_DMA_DATA_WIDTH     = 64
+BSG_MACHINE_NUM_VCACHES_PER_CHANNEL   = 32
 
 BSG_MACHINE_DRAM_SIZE_WORDS           = 536870912
 BSG_MACHINE_DRAM_BANK_SIZE_WORDS      = 16777216
@@ -29,6 +31,7 @@ BSG_MACHINE_HOST_Y_CORD               = 0
 BSG_MACHINE_HOST_X_CORD               = 16
 
 BSG_MACHINE_MEM_CFG                   = e_vcache_hbm2
+BSG_MACHINE_DRAMSIM3_PKG              = bsg_dramsim3_hbm2_8gb_x128_pkg
 
 BSG_MACHINE_SUBARRAY_X                = 1
 BSG_MACHINE_SUBARRAY_Y                = 1

machines/pod_4x4/Makefile.machine.include

@@ -9,10 +9,13 @@ BSG_MACHINE_Y_CORD_WIDTH              = 7
 
 BSG_MACHINE_RUCHE_FACTOR_X            = 3
 
+BSG_MACHINE_NUM_VCACHE_ROWS           = 1
 BSG_MACHINE_VCACHE_SET                = 64
 BSG_MACHINE_VCACHE_WAY                = 4
 BSG_MACHINE_VCACHE_BLOCK_SIZE_WORDS   = 8
 BSG_MACHINE_VCACHE_DMA_DATA_WIDTH     = 32
+BSG_MACHINE_NUM_VCACHES_PER_CHANNEL   = 16
+
 
 BSG_MACHINE_DRAM_SIZE_WORDS           = 536870912
 BSG_MACHINE_DRAM_BANK_SIZE_WORDS      = 16777216
@@ -31,6 +34,7 @@ BSG_MACHINE_HOST_Y_CORD               = 0
 BSG_MACHINE_HOST_X_CORD               = 16
 
 BSG_MACHINE_MEM_CFG                   = e_vcache_test_mem
+BSG_MACHINE_DRAMSIM3_PKG              = bsg_dramsim3_hbm2_8gb_x128_pkg
 
 BSG_MACHINE_SUBARRAY_X                = 1
 BSG_MACHINE_SUBARRAY_Y                = 1

machines/pod_4x4_hbm2/Makefile.machine.include

@@ -9,10 +9,12 @@ BSG_MACHINE_Y_CORD_WIDTH              = 7
 
 BSG_MACHINE_RUCHE_FACTOR_X            = 3
 
-BSG_MACHINE_VCACHE_SET                = 64
+BSG_MACHINE_NUM_VCACHE_ROWS           = 2
 BSG_MACHINE_VCACHE_WAY                = 4
-BSG_MACHINE_VCACHE_BLOCK_SIZE_WORDS   = 8
-BSG_MACHINE_VCACHE_DMA_DATA_WIDTH     = 32
+BSG_MACHINE_VCACHE_SET                = 64
+BSG_MACHINE_VCACHE_BLOCK_SIZE_WORDS   = 16
+BSG_MACHINE_VCACHE_DMA_DATA_WIDTH     = 64
+BSG_MACHINE_NUM_VCACHES_PER_CHANNEL   = 32
 
 BSG_MACHINE_DRAM_SIZE_WORDS           = 536870912
 BSG_MACHINE_DRAM_BANK_SIZE_WORDS      = 16777216
@@ -31,6 +33,7 @@ BSG_MACHINE_HOST_Y_CORD               = 0
 BSG_MACHINE_HOST_X_CORD               = 16
 
 BSG_MACHINE_MEM_CFG                   = e_vcache_hbm2
+BSG_MACHINE_DRAMSIM3_PKG              = bsg_dramsim3_hbm2_8gb_x128_pkg
 
 BSG_MACHINE_SUBARRAY_X                = 1
 BSG_MACHINE_SUBARRAY_Y                = 1

machines/sim_filelist.mk

@@ -44,6 +44,7 @@ CSOURCES += $(BASEJUMP_STL_DIR)/imports/DRAMSim3/src/memory_system.cc
 CSOURCES += $(BASEJUMP_STL_DIR)/imports/DRAMSim3/src/refresh.cc
 CSOURCES += $(BASEJUMP_STL_DIR)/imports/DRAMSim3/src/simple_stats.cc
 CSOURCES += $(BASEJUMP_STL_DIR)/imports/DRAMSim3/src/timing.cc
+CSOURCES += $(BASEJUMP_STL_DIR)/imports/DRAMSim3/src/blood_graph.cc
 
 VSOURCES += $(BASEJUMP_STL_DIR)/bsg_cache/bsg_cache_to_test_dram.v
 VSOURCES += $(BASEJUMP_STL_DIR)/bsg_cache/bsg_cache_to_test_dram_tx.v
@@ -65,6 +66,7 @@ VSOURCES += $(BSG_MANYCORE_DIR)/testbenches/common/v/bsg_nonsynth_manycore_monit
 VSOURCES += $(BSG_MANYCORE_DIR)/testbenches/common/v/bsg_nonsynth_wormhole_test_mem.v
 VSOURCES += $(BSG_MANYCORE_DIR)/testbenches/common/v/bsg_manycore_vcache_wh_to_cache_dma.v
 VSOURCES += $(BSG_MANYCORE_DIR)/testbenches/common/v/bsg_nonsynth_manycore_testbench.v
+VSOURCES += $(BSG_MANYCORE_DIR)/testbenches/common/v/vcache_dma_to_dram_channel_map.v
 VSOURCES += $(BSG_MANYCORE_DIR)/testbenches/common/v/spmd_testbench.v
 
 

software/mk/Makefile.builddefs

@@ -89,6 +89,8 @@ RISCV_GCC_OPTS +=-Dbsg_tiles_X=$(bsg_tiles_X) -Dbsg_tiles_Y=$(bsg_tiles_Y)
 RISCV_GCC_OPTS +=-Dbsg_global_X=$(bsg_global_X) -Dbsg_global_Y=$(bsg_global_Y)
 RISCV_GCC_OPTS +=-Dbsg_group_size=$(bsg_group_size)
 RISCV_GCC_OPTS +=-Dbsg_pods_X=$(bsg_pods_X) -Dbsg_pods_Y=$(bsg_pods_Y)
+RISCV_GCC_OPTS +=-DVCACHE_BLOCK_SIZE_WORDS=${BSG_MACHINE_VCACHE_BLOCK_SIZE_WORDS}
+RISCV_GCC_OPTS +=-DVCACHE_CAPACITY_WORDS=$(shell expr $(BSG_MACHINE_GLOBAL_X) \* $(BSG_MACHINE_VCACHE_SET) \* $(BSG_MACHINE_VCACHE_WAY) \* $(BSG_MACHINE_VCACHE_BLOCK_SIZE_WORDS) \* 2 \* $(BSG_MACHINE_NUM_VCACHE_ROWS))
 
 # IO_X/Y_INDEX indicates global physical coordinate where the host interface is attached.
 # This macros are required by the program to know where to send the finish/fail packets to the host.
@@ -300,7 +302,8 @@ $(BSG_MANYCORE_LIB): $(BSG_MANYCORE_LIB_OBJS)
 		$(bsg_tiles_X) $(bsg_tiles_Y) $(BSG_ELF_OFF_CHIP_MEM) \
 		$(BSG_MACHINE_ORIGIN_X_CORD) $(BSG_MACHINE_ORIGIN_Y_CORD) \
 		$(BSG_MACHINE_PODS_X) $(BSG_MACHINE_PODS_Y) \
-    $(bsg_pods_X) $(bsg_pods_Y) > $*.nbf
+    $(bsg_pods_X) $(bsg_pods_Y) \
+    $(BSG_MACHINE_NUM_VCACHE_ROWS) > $*.nbf
 
 
 %.bin:  %.hex

software/mk/Makefile.dimensions

@@ -3,6 +3,9 @@ bsg_pods_X ?= 1
 bsg_pods_Y ?= 1
 bsg_pods_size ?= $(call bsg-times-fn,$(bsg_pods_X),$(bsg_pods_Y))
 
+# By default, one tile-group running each pod sends exactly one finish packet to the host.
+# The host will wait for the total number of finish packets equal to the number of pods that has spmd programs launched.
+NUM_FINISH ?= $(bsg_pods_size)
 
 # tile-group origin
 # relative to the top-left tile in a pod

software/mk/Makefile.tail_rules

@@ -32,11 +32,17 @@ spike_call_log: pp_spike_trace
 	$(BSG_MANYCORE_DIR)/software/py/func_call_log.py spike_pc.log $(PROG_NAME).riscv > $@
 
 
+# DRAMsim3 blood graph
+dramsim3.%: blood_graph_%.log
+	python $(BSG_MANYCORE_DIR)/software/py/dramsim3_blood_graph.py $< dramsim3_$*.png
+
+
+
 clean:
 	-rm -rf *.o *.a *.jou *.log *.pelog *.pb bsg_manycore_io_complex_rom.v *.riscv *.wdb *.bin *.hex *.ld
 	-rm -rf xsim.dir *.mem stack.info.*
 	-rm -rf ./simv csrc simv.daidir ucli.key DVEfiles *.vpd *.vdb coverage* constfile.txt
 	-rm -rf build/ *.bc* *.ll*
-	-rm -rf lfs.c *.nbf *.csv
-	-rm -rf dramsim3epoch.json pc_stats
+	-rm -rf lfs.c *.nbf *.csv *.png
+	-rm -rf dramsim3epoch.json pc_stats dramsim3.json dramsim3.txt dramsim3.tag.json
 	-rm -rf dis

software/mk/Makefile.verilog

@@ -50,7 +50,7 @@ NBF_FILE = $(PROG_NAME).nbf
 
 BSG_SIM_OPTS = +nbf_file=$(NBF_FILE) \
                +max_cycle=$(MAX_CYCLES) \
-               +num_pods=$(bsg_pods_size) \
+               +num_finish=$(NUM_FINISH) \
                +vanilla_trace_en=$(TRACE) \
                -licqueue -reportstats \
                -l run.log

software/py/dramsim3_blood_graph.py

@@ -0,0 +1,73 @@
+#
+#   dramsim3_blood_graph.py
+#
+#   how to use
+#   python dramsim3_blood_graph.py {input.log}  {output.png}
+#
+#   Author: Tommy
+
+
+
+import sys
+import csv
+from PIL import Image, ImageDraw
+
+class BloodGraph:
+
+  palette = {
+    "act"       : (0xff,0xff,0x00),   ## yellow       = activate
+    "pre"       : (0xff,0xa5,0x00),   ## orange       = precharge
+    "rd"        : (0x00,0xff,0x00),   ## green        = read
+    "wr"        : (0x00,0x88,0x00),   ## dark green   = write
+    "nop"       : (0xff,0xaa,0xff),   ## pink         = no request in this bank
+    "conf"      : (0xff,0x00,0x00),   ## red          = there is a row hit, but can't access due to various timing constraints (tWTR, tCCD_S, etc)
+    "closed"    : (0x80,0x00,0x80),   ## purple       = there is a request in this bank, but the row is closed.
+    "ref"       : (0x60,0x60,0x60),   ## gray         = refresh
+    "arb"       : (0x00,0xff,0xff),   ## cyan         = there is a row hit, but other bank is accessing (arbitrated)
+    "row_miss"  : (0xff,0x00,0xff)    ## fuchsia      = there is a request but row miss.
+  }
+
+  def generate(self, input_file, output_file):
+    traces = []
+    with open(input_file) as f:
+      csv_reader = csv.DictReader(f, delimiter=",")
+      for row in csv_reader:
+        trace = {}
+        trace["time"] = int(row["time"])
+        trace["bank"] = int(row["bank"])
+        trace["state"] = row["state"]
+        traces.append(trace)
+
+      self.__get_stats(traces)
+      self.__init_image()
+      for trace in traces:
+        self.__mark_trace(trace)
+      self.img.save(output_file)
+      return
+
+  def __get_stats(self, traces):
+    banks = list(map(lambda t: t["bank"], traces))
+    times = list(map(lambda t: t["time"], traces))
+    self.num_banks = 1+max(banks)
+    self.end_time = max(times)
+    return
+
+  def __init_image(self):
+    self.img_width = 3900//2
+    self.img_height = ((self.end_time+self.img_width)//self.img_width)*(2+self.num_banks)
+    self.img = Image.new("RGB", (self.img_width, self.img_height), "black")
+    self.pixel = self.img.load()
+    return
+
+  def __mark_trace(self, trace):
+    col = trace["time"] % self.img_width
+    floor = trace["time"] // self.img_width
+    row = floor*(2+self.num_banks) + trace["bank"]
+    self.pixel[col,row] = self.palette[trace["state"]]
+
+
+if __name__ == "__main__":
+  input_file = sys.argv[1]
+  output_file = sys.argv[2]
+  blood_graph = BloodGraph()
+  blood_graph.generate(input_file, output_file)