This repository contains the implementation of a single cycle processor based on the RISC-V ISA. The processor is designed and implemented in two different environments: Logisim and Verilog.
RISC-V ISA: This processor is built to support the RISC-V instruction set architecture, a popular and open standard for instruction set architectures.
Single Cycle Design: The processor follows a single cycle design, making it a simple and educational platform for understanding the principles of processor architecture.
Logisim Implementation: You can explore the processor's functionality and logic in Logisim, a popular educational tool for simulating digital circuits.
Verilog Implementation: For those looking to implement the processor on hardware or in a more realistic setting, a Verilog version is also provided.
To get started with this processor, check out the respective folders for Logisim and Verilog implementations.