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bug fixes
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vaibhawvipul committed Jun 29, 2024
1 parent 14f493a commit 2878d71
Showing 1 changed file with 11 additions and 7 deletions.
18 changes: 11 additions & 7 deletions spark/src/main/scala/org/apache/comet/serde/QueryPlanSerde.scala
Original file line number Diff line number Diff line change
Expand Up @@ -865,7 +865,6 @@ object QueryPlanSerde extends Logging with ShimQueryPlanSerde with CometExprShim
def buildEqualExpr(
leftExpr: Option[Expr],
rightExpr: Option[Expr]): Option[ExprOuterClass.Expr] = {

if (leftExpr.isDefined && rightExpr.isDefined) {
Some(
ExprOuterClass.Expr
Expand All @@ -881,11 +880,10 @@ object QueryPlanSerde extends Logging with ShimQueryPlanSerde with CometExprShim
None
}
}

if (left.dataType == DoubleType ||
left.dataType == FloatType ||
right.dataType == DoubleType ||
right.dataType == FloatType) {
if ((left.dataType == DoubleType &&
right.dataType == DoubleType) ||
(left.dataType == FloatType &&
right.dataType == FloatType)) {
(left, right) match {
case (`negZeroLeft`, `negZeroRight`) =>
return buildEqualExpr(
Expand All @@ -900,8 +898,14 @@ object QueryPlanSerde extends Logging with ShimQueryPlanSerde with CometExprShim
exprToProtoInternal(left, inputs),
exprToProtoInternal(Abs(right).child, inputs))
case _ =>
val doubleNan = Literal(Double.NaN, DoubleType)
val floatNan = Literal(Float.NaN, FloatType)

if ((left.nullable && !right.nullable) &&
(left != leftZero && right != rightZero)) {
(left != negZeroLeft && right != negZeroRight) &&
(left != leftZero && right != rightZero) &&
(left != doubleNan && right != doubleNan) &&
(left != floatNan && right != floatNan)) {
withInfo(expr, left, right)
return None
}
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