valentyusb serial

[mkj]

This adds valentyusb as a uart, works for orangecrab though should be applicable to other platforms.

I'm leaving this as a draft pull request because the software side needs a bit of tidying up - usb_hello is a bit of a demo, really console.c should switch similarly to potato?

It isn't 100% reliable, I have sometimes had the Linux system lock up, yet to debug.

Note that the UART TX will wait forever until a USB host starts reading the USB tty - just "cat /dev/ttyUSBS0" may not be reliable enough and the board will seem to get stuck (screen /dev/ttyUSBS0 works OK).

An early kernel liteuart driver is in mkj/linux@9b3975d

[umarcor]

FTR, stnolting/neorv32#102.

[programmerjake]

I tried this out, to get usb_hello to build, I had to simlink hello_world/head.S into usb_hello.

https://libre-soc.org/irclog/%23libre-soc.2022-03-03.log.html

I didn't get it to work fully:
the USB interface appears to work correctly, and the OrangeCrab's button works, but microwatt appears to never read/write the serial interface.

commands I ran:

(cd usb_hello; ln -s ../hello_world/head.S .; make)
sudo make FPGA_TARGET=ORANGE-CRAB-0.21 dfuprog DOCKER=1 RAM_INIT_FILE=usb_hello/usb_hello.hex MEMORY_SIZE=$((1<<18))

Also, why is usb_hello.elf included in this PR?

[programmerjake]

also, it would probably be useful to have the button reset only microwatt if pressed for a short interval, but also reset the usb interface if pressed for a longer interval, that way you can catch whatever microwatt tries to do immediately after reset, but before the host sets up the usb device.

[mkj]

microwatt appears to never read/write the serial interface.

Ah, it's because by default it builds litedram which doesn't use RAM_INIT_FILE.
I've pushed an update, it should work now:

make FPGA_TARGET=ORANGE-CRAB-0.21 dfuprog DOCKER=1 LITEDRAM_GHDL_ARG=-gUSE_LITEDRAM=false RAM_INIT_FILE=usb_hello/usb_hello.hex MEMORY_SIZE=$((1<<18))

The usb tx on the microwatt side will wait for a host to be attached to the usb serial terminal, so it isn't critical to connect straight away. At some point that would need fixing though.

I've also added head.S and rebased to master branch, seems fine in quick testing (4cf2921 had some changes). I've removed usb_hello.elf.

(unrelated - when I tried a latest docker build, routing was taking hours. Perhaps a recent toolchain update is problematic, an older oss-cad-suite 20220118 is OK here)

[programmerjake]

tested...it works for me now! hopefully I can figure out how to get it to work with litedram though, since I want to try to boot linux at some point, and the fpga's memory is likely too small for that

[mkj]

It will work OK with litedram, just the default litedram init code is using console.c functions which write to uart0 not the usb uart. If you modify console.c so that it calls usb_putchar() instead of putchar() it should print the microwatt "boot loading" messages to the valentyusb. You'll need to rebuild the litedram_core.init by running litedram/gen-src/generate.py - with litex/litex-board/litedram etc in your python path.

Upstream Linux already has a liteuart serial driver, you can enable it in the devicetree with

UARTUSB: usbserial@8000 {
        device_type = "serial";
        compatible = "litex,liteuart";
        reg = <0x8000 0x100>;
        interrupts = <0x15 0x1>;
};

        chosen {
                stdout-path = &UARTUSB;
        }

The branch https://github.com/mkj/linux/commits/matt/orangecrab also has a liteuart driver for powerpc early boot. mkj/linux@9b3975d - not necessary but is useful to see what's going on.

[paulusmack]

It's a pity this doesn't just have a standard 16550 register interface. That would make the software side so much easier.

[programmerjake]

any progress?