Merge pull request #178 from antonblanchard/intercon

Interconnect timing improvements from Ben

common.vhdl

@@ -399,10 +399,6 @@ package common is
 							       write_cr_mask => (others => '0'),
 							       write_cr_data => (others => '0'));
 
-    type XicsToExecute1Type is record
-	irq : std_ulogic;
-    end record;
-
 end common;
 
 package body common is

core.vhdl

@@ -34,7 +34,7 @@ entity core is
 	dmi_wr		: in std_ulogic;
 	dmi_ack	        : out std_ulogic;
 
-	xics_in		: in XicsToExecute1Type;
+	ext_irq		: in std_ulogic;
 
 	terminated_out   : out std_logic
         );
@@ -291,8 +291,8 @@ begin
             flush_out => flush,
 	    stall_out => ex1_stall_out,
             e_in => decode2_to_execute1,
-            i_in => xics_in,
             l_in => loadstore1_to_execute1,
+            ext_irq_in => ext_irq,
             l_out => execute1_to_loadstore1,
             f_out => execute1_to_fetch1,
             e_out => execute1_to_writeback,

core_tb.vhdl

@@ -18,6 +18,8 @@ architecture behave of core_tb is
         -- Dummy DRAM
 	signal wb_dram_in : wishbone_master_out;
 	signal wb_dram_out : wishbone_slave_out;
+	signal wb_dram_ctrl_in : wb_io_master_out;
+	signal wb_dram_ctrl_out : wb_io_slave_out;
 begin
 
     soc0: entity work.soc
@@ -35,6 +37,8 @@ begin
 	    uart0_txd => open,
 	    wb_dram_in => wb_dram_in,
 	    wb_dram_out => wb_dram_out,
+	    wb_dram_ctrl_in => wb_dram_ctrl_in,
+	    wb_dram_ctrl_out => wb_dram_ctrl_out,
 	    alt_reset => '0'
 	    );
 
@@ -59,6 +63,9 @@ begin
     -- Dummy DRAM
     wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
     wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
-    wb_dram_out.stall <= wb_dram_in.cyc and not wb_dram_out.ack;
+    wb_dram_out.stall <= '0';
+    wb_dram_ctrl_out.ack <= wb_dram_ctrl_in.cyc and wb_dram_ctrl_in.stb;
+    wb_dram_ctrl_out.dat <= x"FFFFFFFF";
+    wb_dram_ctrl_out.stall <= '0';
 
 end;

execute1.vhdl

@@ -25,7 +25,7 @@ entity execute1 is
 	e_in  : in Decode2ToExecute1Type;
         l_in  : in Loadstore1ToExecute1Type;
 
-	i_in : in XicsToExecute1Type;
+	ext_irq_in : std_ulogic;
 
 	-- asynchronous
         l_out : out Execute1ToLoadstore1Type;
@@ -419,7 +419,7 @@ begin
 		ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#900#, 64));
 		report "IRQ valid: DEC";
 		irq_valid := '1';
-	    elsif i_in.irq = '1' then
+	    elsif ext_irq_in = '1' then
 		ctrl_tmp.irq_nia <= std_logic_vector(to_unsigned(16#500#, 64));
 		report "IRQ valid: External";
 		irq_valid := '1';

fpga/top-arty.vhdl

@@ -65,11 +65,15 @@ architecture behaviour of toplevel is
     signal system_clk : std_ulogic;
     signal system_clk_locked : std_ulogic;
 
-    -- DRAM wishbone connection
-    signal wb_dram_in   : wishbone_master_out;
-    signal wb_dram_out  : wishbone_slave_out;
-    signal wb_dram_ctrl : std_ulogic;
-    signal wb_dram_init : std_ulogic;
+    -- DRAM main data wishbone connection
+    signal wb_dram_in       : wishbone_master_out;
+    signal wb_dram_out      : wishbone_slave_out;
+
+    -- DRAM control wishbone connection
+    signal wb_dram_ctrl_in  : wb_io_master_out;
+    signal wb_dram_ctrl_out : wb_io_slave_out;
+    signal wb_dram_is_csr   : std_ulogic;
+    signal wb_dram_is_init  : std_ulogic;
 
     -- Control/status
     signal core_alt_reset : std_ulogic;
@@ -104,8 +108,10 @@ begin
 	    uart0_rxd         => uart_main_rx,
 	    wb_dram_in        => wb_dram_in,
 	    wb_dram_out       => wb_dram_out,
-	    wb_dram_ctrl      => wb_dram_ctrl,
-	    wb_dram_init      => wb_dram_init,
+	    wb_dram_ctrl_in   => wb_dram_ctrl_in,
+	    wb_dram_ctrl_out  => wb_dram_ctrl_out,
+	    wb_dram_is_csr    => wb_dram_is_csr,
+	    wb_dram_is_init   => wb_dram_is_init,
 	    alt_reset         => core_alt_reset
 	    );
 
@@ -195,8 +201,10 @@ begin
 
 		wb_in		=> wb_dram_in,
 		wb_out		=> wb_dram_out,
-		wb_is_ctrl      => wb_dram_ctrl,
-		wb_is_init      => wb_dram_init,
+		wb_ctrl_in	=> wb_dram_ctrl_in,
+		wb_ctrl_out	=> wb_dram_ctrl_out,
+		wb_ctrl_is_csr  => wb_dram_is_csr,
+		wb_ctrl_is_init => wb_dram_is_init,
 
 		serial_tx	=> uart_pmod_tx,
 		serial_rx	=> uart_pmod_rx,

fpga/top-generic.vhdl

@@ -33,9 +33,15 @@ architecture behaviour of toplevel is
     signal system_clk : std_ulogic;
     signal system_clk_locked : std_ulogic;
 
-    -- Dummy DRAM
-    signal wb_dram_in : wishbone_master_out;
-    signal wb_dram_out : wishbone_slave_out;
+    -- DRAM main data wishbone connection
+    signal wb_dram_in       : wishbone_master_out;
+    signal wb_dram_out      : wishbone_slave_out;
+
+    -- DRAM control wishbone connection
+    signal wb_dram_ctrl_in  : wb_io_master_out;
+    signal wb_dram_ctrl_out : wb_io_slave_out;
+    signal wb_dram_is_csr   : std_ulogic;
+    signal wb_dram_is_init  : std_ulogic;
 
 begin
 
@@ -79,13 +85,21 @@ begin
 	    rst               => soc_rst,
 	    uart0_txd         => uart0_txd,
 	    uart0_rxd         => uart0_rxd,
+	    wb_dram_in        => wb_dram_in,
 	    wb_dram_out       => wb_dram_out,
+	    wb_dram_ctrl_in   => wb_dram_ctrl_in,
+	    wb_dram_ctrl_out  => wb_dram_ctrl_out,
+	    wb_dram_is_csr    => wb_dram_is_csr,
+	    wb_dram_is_init   => wb_dram_is_init,
 	    alt_reset         => '0'
 	    );
 
     -- Dummy DRAM
     wb_dram_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
     wb_dram_out.dat <= x"FFFFFFFFFFFFFFFF";
     wb_dram_out.stall <= wb_dram_in.cyc and not wb_dram_out.ack;
+    wb_dram_ctrl_out.ack <= wb_dram_in.cyc and wb_dram_in.stb;
+    wb_dram_ctrl_out.dat <= x"FFFFFFFF";
+    wb_dram_ctrl_out.stall <= wb_dram_in.cyc and not wb_dram_out.ack;
 
 end architecture behaviour;

fpga/top-nexys-video.vhdl

@@ -57,11 +57,15 @@ architecture behaviour of toplevel is
     signal system_clk : std_ulogic;
     signal system_clk_locked : std_ulogic;
 
-    -- DRAM wishbone connection
-    signal wb_dram_in   : wishbone_master_out;
-    signal wb_dram_out  : wishbone_slave_out;
-    signal wb_dram_ctrl : std_ulogic;
-    signal wb_dram_init : std_ulogic;
+    -- DRAM main data wishbone connection
+    signal wb_dram_in       : wishbone_master_out;
+    signal wb_dram_out      : wishbone_slave_out;
+
+    -- DRAM control wishbone connection
+    signal wb_dram_ctrl_in  : wb_io_master_out;
+    signal wb_dram_ctrl_out : wb_io_slave_out;
+    signal wb_dram_is_csr   : std_ulogic;
+    signal wb_dram_is_init  : std_ulogic;
 
     -- Control/status
     signal core_alt_reset : std_ulogic;
@@ -87,8 +91,10 @@ begin
 	    uart0_rxd         => uart_main_rx,
 	    wb_dram_in        => wb_dram_in,
 	    wb_dram_out       => wb_dram_out,
-	    wb_dram_ctrl      => wb_dram_ctrl,
-	    wb_dram_init      => wb_dram_init,
+	    wb_dram_ctrl_in   => wb_dram_ctrl_in,
+	    wb_dram_ctrl_out  => wb_dram_ctrl_out,
+	    wb_dram_is_csr    => wb_dram_is_csr,
+	    wb_dram_is_init   => wb_dram_is_init,
 	    alt_reset         => core_alt_reset
 	    );
 
@@ -176,8 +182,10 @@ begin
 
 		wb_in		=> wb_dram_in,
 		wb_out		=> wb_dram_out,
-		wb_is_ctrl      => wb_dram_ctrl,
-		wb_is_init      => wb_dram_init,
+		wb_ctrl_in	=> wb_dram_ctrl_in,
+		wb_ctrl_out	=> wb_dram_ctrl_out,
+		wb_ctrl_is_csr  => wb_dram_is_csr,
+		wb_ctrl_is_init => wb_dram_is_init,
 
 		serial_tx	=> open,
 		serial_rx	=> '0',

include/microwatt_soc.h

@@ -2,9 +2,22 @@
 #define __MICROWATT_SOC_H
 
 /*
- * Definitions for the syscon registers
+ * Microwatt SoC memory map
+ */
+
+#define MEMORY_BASE     0x00000000  /* "Main" memory alias, either BRAM or DRAM */
+#define DRAM_BASE       0x40000000  /* DRAM if present */
+#define BRAM_BASE       0x80000000  /* Internal BRAM */
+
+#define SYSCON_BASE	0xc0000000  /* System control regs */
+#define UART_BASE	0xc0002000  /* UART */
+#define XICS_BASE   	0xc0004000  /* Interrupt controller */
+#define DRAM_CTRL_BASE	0xc0100000  /* LiteDRAM control registers */
+#define DRAM_INIT_BASE  0xf0000000  /* Internal DRAM init firmware */
+
+/*
+ * Register definitions for the syscon registers
  */
-#define SYSCON_BASE	0xc0000000
 
 #define SYS_REG_SIGNATURE		0x00
 #define SYS_REG_INFO			0x08
@@ -18,9 +31,9 @@
 #define   SYS_REG_CTRL_CORE_RESET		(1ull << 1)
 #define   SYS_REG_CTRL_SOC_RESET		(1ull << 2)
 
-/* Definition for the "Potato" UART */
-#define UART_BASE	0xc0002000
-
+/*
+ * Register definitions for the potato UART
+ */
 #define POTATO_CONSOLE_TX		0x00
 #define POTATO_CONSOLE_RX		0x08
 #define POTATO_CONSOLE_STATUS		0x10
@@ -31,7 +44,5 @@
 #define POTATO_CONSOLE_CLOCK_DIV	0x18
 #define POTATO_CONSOLE_IRQ_EN		0x20
 
-/* Definition for the LiteDRAM control registers */
-#define DRAM_CTRL_BASE	0xc0100000
 
 #endif /* __MICROWATT_SOC_H */

litedram/extras/fusesoc-add-files.py

@@ -29,6 +29,8 @@ def run(self):
         files.append({f : {'file_type' : 'verilogSource'}})
         f = os.path.join(gen_dir, "litedram-wrapper.vhdl")
         files.append({f : {'file_type' : 'vhdlSource-2008'}})
+        f = os.path.join(gen_dir, "litedram-initmem.vhdl")
+        files.append({f : {'file_type' : 'vhdlSource-2008'}})
         f = os.path.join(gen_dir, "litedram_core.init")
         files.append({f : {'file_type' : 'user'}})
 

litedram/gen-src/dram-init-mem.vhdl

@@ -0,0 +1,72 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity dram_init_mem is
+    port (
+        clk     : in std_ulogic;
+        wb_in	: in wb_io_master_out;
+        wb_out	: out wb_io_slave_out
+      );
+end entity dram_init_mem;
+
+architecture rtl of dram_init_mem is
+
+    constant INIT_RAM_SIZE : integer := 16384;
+    constant INIT_RAM_ABITS :integer := 14;
+    constant INIT_RAM_FILE : string := "litedram_core.init";
+
+    type ram_t is array(0 to (INIT_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
+
+    impure function init_load_ram(name : string) return ram_t is
+	file ram_file : text open read_mode is name;
+	variable temp_word : std_logic_vector(63 downto 0);
+	variable temp_ram : ram_t := (others => (others => '0'));
+	variable ram_line : line;
+    begin
+	for i in 0 to (INIT_RAM_SIZE/8)-1 loop
+	    exit when endfile(ram_file);
+	    readline(ram_file, ram_line);
+	    hread(ram_line, temp_word);
+	    temp_ram(i*2) := temp_word(31 downto 0);
+	    temp_ram(i*2+1) := temp_word(63 downto 32);
+	end loop;
+	return temp_ram;
+    end function;
+
+    signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE);
+
+    attribute ram_style : string;
+    attribute ram_style of init_ram: signal is "block";
+
+begin
+
+    init_ram_0: process(clk)
+	variable adr : integer;
+    begin
+	if rising_edge(clk) then
+	    wb_out.ack <= '0';
+	    if (wb_in.cyc and wb_in.stb) = '1' then
+		adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2))));
+		if wb_in.we = '0' then
+		    wb_out.dat <= init_ram(adr);
+		else
+		    for i in 0 to 3 loop
+			if wb_in.sel(i) = '1' then
+			    init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
+				wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
+			end if;
+		    end loop;
+		end if;
+		wb_out.ack <= '1';
+	    end if;
+	end if;
+    end process;
+
+    wb_out.stall <= '0';
+
+end architecture rtl;

litedram/gen-src/generate.py

@@ -128,19 +128,23 @@ def generate_one(t, mw_init):
     if mw_init:
         src_wrap_file = os.path.join(gen_src_dir, "wrapper-mw-init.vhdl")
         src_init_file = build_init_code(build_dir)
+        src_initram_file = os.path.join(gen_src_dir, "dram-init-mem.vhdl")
     else:
         write_to_file(os.path.join(t_dir, "init-cpu.txt"), cpu)
         src_wrap_file = os.path.join(gen_src_dir, "wrapper-self-init.vhdl")
         src_init_file = os.path.join(gw_dir, "mem.init")
+        src_initram_file = os.path.join(gen_src_dir, "no-init-mem.vhdl")
 
     # Copy generated files to target dir, amend them if necessary
     core_file = os.path.join(gw_dir, "litedram_core.v")
     dst_init_file = os.path.join(t_dir, "litedram_core.init")
     dst_wrap_file = os.path.join(t_dir, "litedram-wrapper.vhdl")
+    dst_initram_file = os.path.join(t_dir, "litedram-initmem.vhdl")
     replace_in_file(core_file, "mem.init", "litedram_core.init")
     shutil.copy(core_file, t_dir)
     shutil.copyfile(src_init_file, dst_init_file)    
     shutil.copyfile(src_wrap_file, dst_wrap_file)
+    shutil.copyfile(src_initram_file, dst_initram_file)
 
 def main():
 

litedram/gen-src/no-init-mem.vhdl

@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity dram_init_mem is
+    port (
+        clk     : in std_ulogic;
+        wb_in	: in wb_io_master_out;
+        wb_out	: out wb_io_slave_out
+      );
+end entity dram_init_mem;
+
+architecture rtl of dram_init_mem is
+
+    wb_out.dat <= (others => '0');
+    wb_out.stall <= '0';
+    wb_out.ack <= wb_in.stb and wb_in.cyc;
+
+end architecture rtl;