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SPI Engine improvements test #127

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SPI Engine improvements test #127

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db92a7d
SPI Engine: add tb for execution module
LBFFilho Oct 25, 2024
b469eb4
SPI VIP: minor cleanup
LBFFilho Oct 25, 2024
aa4b111
SPI Engine: add sw control for sdo source
LBFFilho Sep 6, 2024
6641981
SPI Engine: improve cfg, add test_slowdata
LBFFilho Nov 29, 2024
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11 changes: 9 additions & 2 deletions library/regmaps/adi_regmap_spi_engine_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@
// ***************************************************************************
// ***************************************************************************
/* Auto generated Register Map */
/* Wed Jul 24 09:28:37 2024 */
/* Tue Oct 29 19:18:58 2024 */

package adi_regmap_spi_engine_pkg;
import adi_regmap_pkg::*;
Expand All @@ -43,7 +43,7 @@ package adi_regmap_spi_engine_pkg;

const reg_t AXI_SPI_ENGINE_VERSION = '{ 'h0000, "VERSION" , '{
"VERSION_MAJOR": '{ 31, 16, RO, 'h00000001 },
"VERSION_MINOR": '{ 15, 8, RO, 'h00000003 },
"VERSION_MINOR": '{ 15, 8, RO, 'h00000004 },
"VERSION_PATCH": '{ 7, 0, RO, 'h00000001 }}};
`define SET_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR(x) SetField(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR",x)
`define GET_AXI_SPI_ENGINE_VERSION_VERSION_MAJOR(x) GetField(AXI_SPI_ENGINE_VERSION,"VERSION_MAJOR",x)
Expand Down Expand Up @@ -257,6 +257,13 @@ package adi_regmap_spi_engine_pkg;
`define DEFAULT_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET GetResetValue(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET,"OFFLOAD0_MEM_RESET")
`define UPDATE_AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET_OFFLOAD0_MEM_RESET(x,y) UpdateField(AXI_SPI_ENGINE_OFFLOAD0_MEM_RESET,"OFFLOAD0_MEM_RESET",x,y)

const reg_t AXI_SPI_ENGINE_OFFLOAD0_SDO_SRC_SEL = '{ 'h010c, "OFFLOAD0_SDO_SRC_SEL" , '{
"OFFLOAD0_SDO_SRC_SEL": '{ 31, 0, RW, 'h00000000 }}};
`define SET_AXI_SPI_ENGINE_OFFLOAD0_SDO_SRC_SEL_OFFLOAD0_SDO_SRC_SEL(x) SetField(AXI_SPI_ENGINE_OFFLOAD0_SDO_SRC_SEL,"OFFLOAD0_SDO_SRC_SEL",x)
`define GET_AXI_SPI_ENGINE_OFFLOAD0_SDO_SRC_SEL_OFFLOAD0_SDO_SRC_SEL(x) GetField(AXI_SPI_ENGINE_OFFLOAD0_SDO_SRC_SEL,"OFFLOAD0_SDO_SRC_SEL",x)
`define DEFAULT_AXI_SPI_ENGINE_OFFLOAD0_SDO_SRC_SEL_OFFLOAD0_SDO_SRC_SEL GetResetValue(AXI_SPI_ENGINE_OFFLOAD0_SDO_SRC_SEL,"OFFLOAD0_SDO_SRC_SEL")
`define UPDATE_AXI_SPI_ENGINE_OFFLOAD0_SDO_SRC_SEL_OFFLOAD0_SDO_SRC_SEL(x,y) UpdateField(AXI_SPI_ENGINE_OFFLOAD0_SDO_SRC_SEL,"OFFLOAD0_SDO_SRC_SEL",x,y)

const reg_t AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO = '{ 'h0110, "OFFLOAD0_CDM_FIFO" , '{
"OFFLOAD0_CDM_FIFO": '{ 31, 0, WO, 'hXXXXXXXX }}};
`define SET_AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO_OFFLOAD0_CDM_FIFO(x) SetField(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO,"OFFLOAD0_CDM_FIFO",x)
Expand Down
2 changes: 0 additions & 2 deletions library/vip/adi/spi_vip/adi_spi_vip.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -33,8 +33,6 @@
// ***************************************************************************
// ***************************************************************************

`include "utils.svh"

module adi_spi_vip #(
parameter MODE = 0, // SLAVE=0
parameter CPOL = 0,
Expand Down
3 changes: 1 addition & 2 deletions library/vip/adi/spi_vip/adi_spi_vip_ip.tcl
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Expand Up @@ -8,7 +8,6 @@ source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl

adi_ip_create adi_spi_vip
adi_ip_files adi_spi_vip [list \
"adi_spi_vip_pkg.sv" \
"adi_spi_vip.sv" \
"spi_vip_if.sv" \
"adi_spi_vip_pkg.ttcl" \
Expand Down Expand Up @@ -157,7 +156,7 @@ set_property -dict [list \
## DEFAULT_MISO_DATA
set_property -dict [list \
"value_bit_string_length" "32" \
"value_format" "bit_string" \
"value_format" "bitString" \
"enablement_tcl_expr" "\$MODE==0" \
] \
[ipx::get_user_parameters DEFAULT_MISO_DATA -of_objects $cc]
Expand Down
10 changes: 10 additions & 0 deletions library/vip/amd/s_axis_sequencer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -140,6 +140,16 @@ package s_axis_sequencer_pkg;
end
endtask

// function for popping bytes that the test doesn't care about
task get_byte(
output bit [7:0] data);
if (byte_stream.size() == 0) begin
`ERROR(("Byte steam empty !!!"));
end else begin
data = byte_stream.pop_front();
end
endtask

// call ready generation function
task run();
user_gen_tready();
Expand Down
58 changes: 58 additions & 0 deletions testbenches/ip/spi_engine/cfgs/cfg00.tcl
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Original file line number Diff line number Diff line change
@@ -0,0 +1,58 @@
global ad_project_params

# SPI Engine DUT parameters
set ad_project_params(DATA_WIDTH) 32
set ad_project_params(ASYNC_SPI_CLK) 1
set ad_project_params(NUM_OF_CS) 1
set ad_project_params(NUM_OF_SDI) 1
set ad_project_params(NUM_OF_SDO) 1
set ad_project_params(SDI_DELAY) 1
set ad_project_params(ECHO_SCLK) 0
set ad_project_params(CMD_MEM_ADDR_WIDTH) 4
set ad_project_params(DATA_MEM_ADDR_WIDTH) 4
set ad_project_params(SDI_FIFO_ADDR_WIDTH) 5
set ad_project_params(SDO_FIFO_ADDR_WIDTH) 5
set ad_project_params(SYNC_FIFO_ADDR_WIDTH) 4
set ad_project_params(CMD_FIFO_ADDR_WIDTH) 4
set ad_project_params(SDO_STREAMING) 0

# Test parameters
set ad_project_params(DATA_DLENGTH) 16
set ad_project_params(THREE_WIRE) 0
set ad_project_params(CPOL) 0
set ad_project_params(CPHA) 0
set ad_project_params(SDO_IDLE_STATE) 0
set ad_project_params(SLAVE_TIN) 0
set ad_project_params(SLAVE_TOUT) 0
set ad_project_params(MASTER_TIN) 0
set ad_project_params(MASTER_TOUT) 0
set ad_project_params(CS_TO_MISO) 0
set ad_project_params(CLOCK_DIVIDER) 2
set ad_project_params(NUM_OF_WORDS) 5
set ad_project_params(NUM_OF_TRANSFERS) 5
set ad_project_params(CS_ACTIVE_HIGH) 0
set ad_project_params(ECHO_SCLK_DELAY) 0.1

set spi_s_vip_cfg [ list \
MODE 0 \
CPOL $ad_project_params(CPOL) \
CPHA $ad_project_params(CPHA) \
INV_CS $ad_project_params(CS_ACTIVE_HIGH) \
SLAVE_TIN $ad_project_params(SLAVE_TIN) \
SLAVE_TOUT $ad_project_params(SLAVE_TOUT) \
MASTER_TIN $ad_project_params(MASTER_TIN) \
MASTER_TOUT $ad_project_params(MASTER_TOUT) \
CS_TO_MISO $ad_project_params(CS_TO_MISO) \
DATA_DLENGTH $ad_project_params(DATA_DLENGTH) \
]
set ad_project_params(spi_s_vip_cfg) $spi_s_vip_cfg

set axis_sdo_src_vip_cfg [ list \
INTERFACE_MODE {MASTER} \
HAS_TREADY 1 \
HAS_TLAST 0 \
TDATA_NUM_BYTES [expr $ad_project_params(DATA_WIDTH)/8] \
TDEST_WIDTH 0 \
TID_WIDTH 0 \
]
set ad_project_params(axis_sdo_src_vip_cfg) $axis_sdo_src_vip_cfg
1 change: 0 additions & 1 deletion testbenches/ip/spi_engine/cfgs/cfg1.tcl → testbenches/ip/spi_engine/cfgs/cfg01.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,6 @@ set ad_project_params(NUM_OF_WORDS) 3
set ad_project_params(NUM_OF_TRANSFERS) 5
set ad_project_params(CS_ACTIVE_HIGH) 0
set ad_project_params(ECHO_SCLK_DELAY) 0.1
set ad_project_params(SDO_MEM_WORDS) 1

set spi_s_vip_cfg [ list \
MODE 0 \
Expand Down
58 changes: 58 additions & 0 deletions testbenches/ip/spi_engine/cfgs/cfg10.tcl
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Original file line number Diff line number Diff line change
@@ -0,0 +1,58 @@
global ad_project_params

# SPI Engine DUT parameters
set ad_project_params(DATA_WIDTH) 32
set ad_project_params(ASYNC_SPI_CLK) 1
set ad_project_params(NUM_OF_CS) 1
set ad_project_params(NUM_OF_SDI) 1
set ad_project_params(NUM_OF_SDO) 1
set ad_project_params(SDI_DELAY) 1
set ad_project_params(ECHO_SCLK) 0
set ad_project_params(CMD_MEM_ADDR_WIDTH) 4
set ad_project_params(DATA_MEM_ADDR_WIDTH) 4
set ad_project_params(SDI_FIFO_ADDR_WIDTH) 5
set ad_project_params(SDO_FIFO_ADDR_WIDTH) 5
set ad_project_params(SYNC_FIFO_ADDR_WIDTH) 4
set ad_project_params(CMD_FIFO_ADDR_WIDTH) 4
set ad_project_params(SDO_STREAMING) 0

# Test parameters
set ad_project_params(DATA_DLENGTH) 18
set ad_project_params(THREE_WIRE) 0
set ad_project_params(CPOL) 1
set ad_project_params(CPHA) 0
set ad_project_params(SDO_IDLE_STATE) 0
set ad_project_params(SLAVE_TIN) 0
set ad_project_params(SLAVE_TOUT) 0
set ad_project_params(MASTER_TIN) 0
set ad_project_params(MASTER_TOUT) 0
set ad_project_params(CS_TO_MISO) 0
set ad_project_params(CLOCK_DIVIDER) 2
set ad_project_params(NUM_OF_WORDS) 3
set ad_project_params(NUM_OF_TRANSFERS) 5
set ad_project_params(CS_ACTIVE_HIGH) 0
set ad_project_params(ECHO_SCLK_DELAY) 0.1

set spi_s_vip_cfg [ list \
MODE 0 \
CPOL $ad_project_params(CPOL) \
CPHA $ad_project_params(CPHA) \
INV_CS $ad_project_params(CS_ACTIVE_HIGH) \
SLAVE_TIN $ad_project_params(SLAVE_TIN) \
SLAVE_TOUT $ad_project_params(SLAVE_TOUT) \
MASTER_TIN $ad_project_params(MASTER_TIN) \
MASTER_TOUT $ad_project_params(MASTER_TOUT) \
CS_TO_MISO $ad_project_params(CS_TO_MISO) \
DATA_DLENGTH $ad_project_params(DATA_DLENGTH) \
]
set ad_project_params(spi_s_vip_cfg) $spi_s_vip_cfg

set axis_sdo_src_vip_cfg [ list \
INTERFACE_MODE {MASTER} \
HAS_TREADY 1 \
HAS_TLAST 0 \
TDATA_NUM_BYTES [expr $ad_project_params(DATA_WIDTH)/8] \
TDEST_WIDTH 0 \
TID_WIDTH 0 \
]
set ad_project_params(axis_sdo_src_vip_cfg) $axis_sdo_src_vip_cfg
58 changes: 58 additions & 0 deletions testbenches/ip/spi_engine/cfgs/cfg11.tcl
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Original file line number Diff line number Diff line change
@@ -0,0 +1,58 @@
global ad_project_params

# SPI Engine DUT parameters
set ad_project_params(DATA_WIDTH) 32
set ad_project_params(ASYNC_SPI_CLK) 1
set ad_project_params(NUM_OF_CS) 1
set ad_project_params(NUM_OF_SDI) 1
set ad_project_params(NUM_OF_SDO) 1
set ad_project_params(SDI_DELAY) 1
set ad_project_params(ECHO_SCLK) 0
set ad_project_params(CMD_MEM_ADDR_WIDTH) 4
set ad_project_params(DATA_MEM_ADDR_WIDTH) 4
set ad_project_params(SDI_FIFO_ADDR_WIDTH) 5
set ad_project_params(SDO_FIFO_ADDR_WIDTH) 5
set ad_project_params(SYNC_FIFO_ADDR_WIDTH) 4
set ad_project_params(CMD_FIFO_ADDR_WIDTH) 4
set ad_project_params(SDO_STREAMING) 0

# Test parameters
set ad_project_params(DATA_DLENGTH) 18
set ad_project_params(THREE_WIRE) 0
set ad_project_params(CPOL) 1
set ad_project_params(CPHA) 1
set ad_project_params(SDO_IDLE_STATE) 0
set ad_project_params(SLAVE_TIN) 0
set ad_project_params(SLAVE_TOUT) 0
set ad_project_params(MASTER_TIN) 0
set ad_project_params(MASTER_TOUT) 0
set ad_project_params(CS_TO_MISO) 0
set ad_project_params(CLOCK_DIVIDER) 2
set ad_project_params(NUM_OF_WORDS) 3
set ad_project_params(NUM_OF_TRANSFERS) 5
set ad_project_params(CS_ACTIVE_HIGH) 0
set ad_project_params(ECHO_SCLK_DELAY) 0.1

set spi_s_vip_cfg [ list \
MODE 0 \
CPOL $ad_project_params(CPOL) \
CPHA $ad_project_params(CPHA) \
INV_CS $ad_project_params(CS_ACTIVE_HIGH) \
SLAVE_TIN $ad_project_params(SLAVE_TIN) \
SLAVE_TOUT $ad_project_params(SLAVE_TOUT) \
MASTER_TIN $ad_project_params(MASTER_TIN) \
MASTER_TOUT $ad_project_params(MASTER_TOUT) \
CS_TO_MISO $ad_project_params(CS_TO_MISO) \
DATA_DLENGTH $ad_project_params(DATA_DLENGTH) \
]
set ad_project_params(spi_s_vip_cfg) $spi_s_vip_cfg

set axis_sdo_src_vip_cfg [ list \
INTERFACE_MODE {MASTER} \
HAS_TREADY 1 \
HAS_TLAST 0 \
TDATA_NUM_BYTES [expr $ad_project_params(DATA_WIDTH)/8] \
TDEST_WIDTH 0 \
TID_WIDTH 0 \
]
set ad_project_params(axis_sdo_src_vip_cfg) $axis_sdo_src_vip_cfg
1 change: 0 additions & 1 deletion testbenches/ip/spi_engine/cfgs/cfg_inv_cs.tcl
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Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,6 @@ set ad_project_params(NUM_OF_WORDS) 3
set ad_project_params(NUM_OF_TRANSFERS) 5
set ad_project_params(CS_ACTIVE_HIGH) 1
set ad_project_params(ECHO_SCLK_DELAY) 0.1
set ad_project_params(SDO_MEM_WORDS) 2

set spi_s_vip_cfg [ list \
MODE 0 \
Expand Down
1 change: 0 additions & 1 deletion testbenches/ip/spi_engine/cfgs/cfg_sdo_streaming.tcl
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Expand Up @@ -32,7 +32,6 @@ set ad_project_params(NUM_OF_WORDS) 5
set ad_project_params(NUM_OF_TRANSFERS) 3
set ad_project_params(CS_ACTIVE_HIGH) 0
set ad_project_params(ECHO_SCLK_DELAY) 0.1
set ad_project_params(SDO_MEM_WORDS) 2

set spi_s_vip_cfg [ list \
MODE 0 \
Expand Down
1 change: 1 addition & 0 deletions testbenches/ip/spi_engine/system_project.tcl
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Expand Up @@ -44,6 +44,7 @@ adi_sim_project_files [list \
"spi_environment.sv" \
"tests/test_program.sv" \
"tests/test_sleep_delay.sv" \
"tests/test_slowdata.sv" \
"system_tb.sv" \
]

Expand Down
28 changes: 16 additions & 12 deletions testbenches/ip/spi_engine/tests/test_program.sv
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Expand Up @@ -274,8 +274,6 @@ bit [`DATA_DLENGTH-1:0] sdi_read_data_store [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)
bit [`DATA_DLENGTH-1:0] sdo_write_data_store [(`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS) -1 :0];
bit [`DATA_DLENGTH-1:0] rx_data;
bit [`DATA_DLENGTH-1:0] tx_data;
localparam sdo_mem_num = (`SDO_STREAMING) ? (`MIN((`NUM_OF_WORDS),(`SDO_MEM_WORDS))) : (`NUM_OF_WORDS);
bit [`DATA_DLENGTH-1:0] one_shot_sdo_data [sdo_mem_num-1 :0] = '{default:'0};

task offload_spi_test();
//Configure DMA
Expand All @@ -288,6 +286,11 @@ task offload_spi_test();
env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_DEST_ADDRESS), `SET_DMAC_DEST_ADDRESS_DEST_ADDRESS(`DDR_BA));
env.mng.RegWrite32(`SPI_ENGINE_DMA_BA + GetAddrs(DMAC_TRANSFER_SUBMIT), `SET_DMAC_TRANSFER_SUBMIT_TRANSFER_SUBMIT(1));

`ifdef DEF_SDO_STREAMING
// Enable SDO Offload
axi_write(`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_SDO_SRC_SEL), `SET_AXI_SPI_ENGINE_OFFLOAD0_SDO_SRC_SEL_OFFLOAD0_SDO_SRC_SEL(1));
`endif

// Configure the Offload module
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_CFG);
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_PRESCALE);
Expand All @@ -301,21 +304,22 @@ task offload_spi_test();
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_CDM_FIFO), `INST_SYNC | 2);

// Enqueue transfers transfers to DUT
for (int i = 0; i<sdo_mem_num; i=i+1) begin
one_shot_sdo_data[i] = $urandom;
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO), one_shot_sdo_data[i]);
end
for (int i = 0; i<((`NUM_OF_TRANSFERS)*(`NUM_OF_WORDS)) ; i=i+1) begin
rx_data = $urandom;
spi_send(rx_data);
sdi_read_data_store[i] = rx_data;
if (i%(`NUM_OF_WORDS)<sdo_mem_num) begin
tx_data = one_shot_sdo_data[i%(`NUM_OF_WORDS)];
end else begin
tx_data = $urandom;
tx_data = $urandom;
`ifdef DEF_SDO_STREAMING
sdo_stream_gen(tx_data);
end
sdo_write_data_store[i] = tx_data;
sdo_write_data_store[i] = tx_data;
`else
if (i<(`NUM_OF_WORDS)) begin
sdo_write_data_store[i] = tx_data;
axi_write (`SPI_ENGINE_SPI_REGMAP_BA + GetAddrs(AXI_SPI_ENGINE_OFFLOAD0_SDO_FIFO), sdo_write_data_store[i]);
end else begin
sdo_write_data_store[i] = sdo_write_data_store[i%(`NUM_OF_WORDS)];
end
`endif
end

// Start the offload
Expand Down
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