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Util axis fifo asym #1287
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Util axis fifo asym #1287
Commits on Sep 10, 2024
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ad_mem: Added initialization with 0 at startup for simulations
Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
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util_axis_fifo_asym: Bugfix and update
- Fixed a bug where datapaths with different widths caused data corruption - Added an option to manually restrict certain parameter values based on the datapath widths Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
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- Added additional perspective option for the address - Updated the IPs that are affected Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
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util_axis_fifo_asym: Updated copyright year
Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
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- Rounded up the almost empty and full threshold values - Fixed the tlast signal on the master side Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
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util_axis_fifo: Fixed tkeep bit width
Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
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util_axis_fifo_asym: Fixed a couple of specific cases
Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
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Commits on Sep 26, 2024
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util_axis_fifo_asym: Master interface functional change
Condition: master data width < slave data width, keep and last are enabled: If there are atomic FIFOs that have all keep bits set to 0, their data is not sent and tlast is generated on the last atomic FIFO transfer that had valid keep bits Atomic transfers that have all keep bits set to 0 are activated, but the valid and the appropriate tlast signal is retained Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
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Commits on Oct 8, 2024
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util_axis_fifo_asym: Guideline check fix
Signed-off-by: Istvan-Zsolt Szekely <[email protected]>
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