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Initial support for gowin vendor via proprietary and apicula toolchain. #734

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merged 1 commit into from
Aug 8, 2023

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bl0x
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@bl0x bl0x commented Dec 20, 2022

Supported devices: gw1n 9c / tang nano 9k

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@whitequark
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Does the Apicula toolchain not support IOB registers at all currently?

@bl0x
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bl0x commented Dec 22, 2022

Unclear. The blinky did not want them. I can check how far it goes. @pepijndevos certainly knows more. Also, the fuzzer code mentions IOBUF.

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I will merge the PR once all of the features of the Apicula toolchain are supported, similar to Lattice, Xilinx, etc ones.

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codecov-commenter commented Dec 22, 2022

Codecov Report

Merging #734 (512d8bf) into main (b952005) will not change coverage.
Report is 1 commits behind head on main.
The diff coverage is n/a.

❗ Current head 512d8bf differs from pull request most recent head efc0860. Consider uploading reports for the commit efc0860 to get more accurate results

@@           Coverage Diff           @@
##             main     #734   +/-   ##
=======================================
  Coverage   82.74%   82.74%           
=======================================
  Files          52       52           
  Lines        7089     7089           
  Branches     1705     1705           
=======================================
  Hits         5866     5866           
+ Misses       1025     1024    -1     
- Partials      198      199    +1     

see 1 file with indirect coverage changes

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Exciting stuff. Looks like the IOB question has been resolved right?

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bl0x commented Dec 22, 2022

@pepijndevos thanks! What else is supported in apicula? Is there a list of supported and tested primitives somewhere?

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Tested you say? Bwaha
There is https://github.com/YosysHQ/yosys/wiki/FPGA-family-feature-matrix
Recent development is WIP pll support but not on 9k yet.

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bl0x commented Dec 22, 2022

Ok, so DDR is something I could at least add and see if it compiles.

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bl0x commented Jan 17, 2023

I've rebased and added support for xdr>0 from https://github.com/tcjie/Gowin repo.
The next step could be to also add support for the vendor toolchain that is also included in tcjie's repo.
@tcjie: would you want to contribute?

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bl0x commented Jan 24, 2023

@pepijndevos if you have time, could you perhaps have a look here? Is anything still missing? Testing is still pending for the differential IO, since I have limited means to do this.

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tcjie commented Jan 25, 2023

@bl0x The answer is yes.

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Eh, not too familiar with amaranth but I guess it basically looks fine. What do you need for testing differential IO? IIRC we basically run this example as a sanity check https://github.com/YosysHQ/apicula/blob/master/examples/blinky-oddr.v

@bl0x bl0x force-pushed the support-gw1n-9c branch from 53746fa to 166ba11 Compare March 29, 2023 19:01
@bl0x bl0x changed the title Initial support for gowin vendor via apicula toolchain. Initial support for gowin vendor via proprietary and apicula toolchain. Apr 6, 2023
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bl0x commented Apr 6, 2023

@tcjie I've used some code from your repository https://github.com/tcjie/Gowin to add support for the proprietary gowin toolchain.

@bl0x bl0x requested a review from whitequark April 12, 2023 17:49
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bl0x commented Apr 12, 2023

Support for on chip oscillators is now also in.

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josuah commented Apr 17, 2023

Here is the result with pip install . on bl0x's fork of amaranth (this branch) then running:

$ python amaranth_boards/tang_nano_9k.py
Jtag frequency : requested 6.00MHz   -> real 6.00MHz
Parse file Parse /tmp/amaranth_j3bogl4d_top.fs:
Done
DONE
Jtag frequency : requested 2.50MHz   -> real 2.00MHz
erase SRAM Done
Flash SRAM: [==================================================] 100.00%
Done
$

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josuah commented Apr 17, 2023

Exact same result as above with the Gowin toolchain, after doing this:

# ln -sf /opt/Gowin_V1.9.8.09_linux/IDE/bin/gw_sh /usr/local/bin

test.py

from amaranth_boards.tang_nano_9k import *
from amaranth_boards.test.blinky import *
TangNano9kPlatform(toolchain="Gowin").build(Blinky(), do_program=True)
$ python test.py
*** GOWIN Tcl Command Line Console  ***
add new file: "top.v"
add new file: "top.cst"
add new file: "top.sdc"
current device: GW1NR-9C  GW1NR-LV9QN88PC6/I5
GowinSynthesis start
Running parser ...
Analyzing Verilog file '/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v'
Compiling module 'top'("/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v":160)
WARN  (EX3780) : Using initial value of '$auto$verilog_backend.cc:2083:dump_module$2' since it is never assigned("/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v":161)
Compiling module 'cd_sync'("/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v":4)
Compiling module 'reset_sync'("/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v":119)
WARN  (EX3780) : Using initial value of '$auto$verilog_backend.cc:2083:dump_module$1' since it is never assigned("/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v":120)
Compiling module 'pin_button_0'("/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v":19)
Compiling module 'pin_button_1'("/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v":30)
Compiling module 'pin_clk27_0'("/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v":41)
Compiling module 'pin_led_0'("/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v":53)
Compiling module 'pin_led_1'("/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v":64)
Compiling module 'pin_led_2'("/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v":75)
Compiling module 'pin_led_3'("/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v":86)
Compiling module 'pin_led_4'("/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v":97)
Compiling module 'pin_led_5'("/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.v":108)
NOTE  (EX0101) : Current top module is "top"
[5%] Running netlist conversion ...
Running device independent optimization ...
[10%] Optimizing Phase 0 completed
[15%] Optimizing Phase 1 completed
[25%] Optimizing Phase 2 completed
Running inference ...
[30%] Inferring Phase 0 completed
[40%] Inferring Phase 1 completed
[50%] Inferring Phase 2 completed
[55%] Inferring Phase 3 completed
Running technical mapping ...
[60%] Tech-Mapping Phase 0 completed
[65%] Tech-Mapping Phase 1 completed
[75%] Tech-Mapping Phase 2 completed
[80%] Tech-Mapping Phase 3 completed
[90%] Tech-Mapping Phase 4 completed
[95%] Generate netlist file "/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/impl/gwsynthesis/project.vg" completed
[100%] Generate report file "/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/impl/gwsynthesis/project_syn.rpt.html" completed
GowinSynthesis finish
Reading netlist file: "/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/impl/gwsynthesis/project.vg"
Parsing netlist file "/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/impl/gwsynthesis/project.vg" completed
Processing netlist completed
Reading constraint file: "/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/top.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/impl/pnr/project.power.html" completed
Generate file "/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/impl/pnr/project.pin.html" completed
Generate file "/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/impl/pnr/project.rpt.html" completed
Generate file "/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/impl/pnr/project.rpt.txt" completed
Generate file "/home/josuah/amaranth-lang/amaranth-boards-bl0x/build/impl/pnr/project.tr.html" completed
Mon Apr 17 17:14:17 2023

Jtag frequency : requested 6.00MHz   -> real 6.00MHz
Parse file Parse /tmp/amaranth_5xhumiex_top.fs:
Done
DONE
Jtag frequency : requested 2.50MHz   -> real 2.00MHz
erase SRAM Done
Flash SRAM: [==================================================] 100.00%
Done
$ 

@tcjie
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tcjie commented Apr 21, 2023

@bl0x that's very useful

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Thank you for your contribution! I do not see any technical issues with this PR. I'm going to test it locally and once everything passes, merge it.

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On second look I was a bit too enthusiastic earlier, sorry about that!

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bl0x commented Aug 8, 2023

part and family are needed to unambiguously fix the part. I've gone through device_list.csv that comes with Gowin IDE and checked. Neither part nor family alone has the full information needed.

Therefore, it is probably best (now and for the future) to use these two as input and check that they are somwhat sane and at least agree with each other.


To make a parts list in python use this gist.
Then use this to check that all families and parts can be matched with the regexes.

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bl0x commented Aug 8, 2023

@whitequark I'm happier now with the PR =)
Thanks for all the comments.

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@bl0x Thanks so much, you're a hero! I did one last round of small changes, mostly focused on making the regexp use a little more idiomatic, though I think "\d" will become invalid in newer Python versions as well so it has to be r"\d".

Could you check that my edits are correct? Then I'm happy to merge this at last!

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Really happy with this PR!

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All fine with me! Thanks!

It's good to go then?

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@bl0x Yep! I'm going to squash all the commits in this PR and then merge.

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@bl0x Actually, I'm hitting an odd issue with hardware testing. I'm using this Tang Nano platform file and it just doesn't blink at all. Do you know why?

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bl0x commented Aug 8, 2023

Did it blink before at all? You've showed some video demo before. Was that the same device?

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I've never used the built-in oscillator before since it was kind of awkward. I decided to try it out now that the support for it seems to be done properly.

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bl0x commented Aug 8, 2023

I'll try and check with tang nano 9k later.

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bl0x commented Aug 8, 2023

Using "OSC" and 25 MHz with tang nano 9k the 6 LEDs flash.
No buttons pressed: LED 0 and 1 are inverted vs. the rest
Buttons pressed: All LEDs flash with same phase.

With 12.5 MHz the flash speed increases (by factor 2?)
With 62.5 MHz the flash speed decreases (also by a factor of ~2), now at ~8 Hz toggle rate.

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No buttons pressed: LED 0 and 1 are inverted vs. the rest

This means you need to pass invert=True to the button resource.

With 12.5 MHz the flash speed increases (by factor 2?) With 62.5 MHz the flash speed decreases (also by a factor of ~2), now at ~8 Hz toggle rate.

This seems wrong; the LEDs are supposed to always flash with 1 Hz period.

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This looks like an upstream bug: YosysHQ/apicula#193

@bl0x I'll fix the filename overwrite issue. Could you take a look at why blinky doesn't get the right frequency?

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As blinky works on both 1k and 9k, I'm merging this 🎉

@whitequark whitequark enabled auto-merge August 8, 2023 12:33
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bl0x commented Aug 8, 2023

@whitequark nice work!

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Thank you!

@whitequark whitequark added this pull request to the merge queue Aug 8, 2023
Merged via the queue into amaranth-lang:main with commit 93e89f5 Aug 8, 2023
self.package = match.group(5)
self.speed = match.group(6)

match = re.match(reg_series+reg_size+reg_subseries+"$", self.family)
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Hold on. This matches series, size, and subseries, all of which are also matched above. So what information does family actually add?

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It's... Complicated. Iirc device names don't actually uniquely define the actual device. I think I have an email from their support that's supposed to explain it but honestly it just doesn't make any sense.

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Have you looked at the code here?

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So this suggests there could be a "series" in the part name that is not the same as the "series_f" in the part family?

In the datasheet, "Family" seems to be LittleBee or Arora, and "Series" seems to be names like "GW1N"

For convenience:
http://cdn.gowinsemi.com.cn/DS100E.pdf#page=85

2023-08-10-202234_726x818_scrot

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It might be related to revisions of the chips, as shown on the package marking, as opposed to the datasheets:

https://github.com/brilliantlabsAR/docs/blob/e075bbe5784e6a61d23e10cbb86e26fe74a1831b/monocle/monocle.md#fpga-chip-revisions

So while a full part order name might be GW1N-LV9 MG100C6/I5 the device family name as shown in GOWIN EDA software tool might be different according to... the extra chip marking information "xxxxCA0N" also shown here: GW1N-9C

Many thanks to @siliconwitch who found out about it.

And as you can see, this would also have a different Device ID.

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@josuah That is exactly why I'm doing the double-matching and why one also has to supply family to uniquely identify the part.

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Just take a look at the contents of <path-to-gowin-IDE>/share/device/device_info.csv.
Run this:

awk -F"," '{print $2}' device_info.csv | sort | uniq -c

and you'll see that the part name in column 2 is not unique enough.

You need in addition the family name in column 4. The below command returns 0 lines:

awk -F"," '{print $2, $4}' device_info.csv | sort | uniq -c | awk '$1!=1' | wc -l

while the not taking into account the family name gives >100 non-unique parts:

awk -F"," '{print $2}' device_info.csv | sort | uniq -c | awk '$1!=1' | wc -l

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And the device family lacks the package information used for the pin mapping.

I suppose they would have preferred to avoid this split themselves.
Maybe a difference in the process with the same masks.
Maybe a fix that lead to more consequences than intended.

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@bl0x But the RE that matches family is a subset of the RE that matches part... what am I missing?

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@whitequark Nothing! Because part can also contain all information (and oftentimes does), but not always. We could use the same RE to also match family, but that would be too general.

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