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Merge pull request #295 from yrabbit/iodelay
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Add IODELAY.
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@yrabbit
yrabbit authored Dec 13, 2024
2 parents 81ab31a + 5cc2502 commit 3c154d0
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Showing 11 changed files with 138 additions and 35 deletions.
68 changes: 46 additions & 22 deletions apycula/gowin_pack.py
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Original file line number Diff line number Diff line change
Expand Up @@ -2077,6 +2077,7 @@ def set_hclk_attrs(db, params, num, typ, cell_name):
'IOLOGIC': {},
'IOLOGIC_DUMMY': {},
'IOLOGICI_EMPTY': {'GSREN': 'false', 'LSREN': 'true'},
'IOLOGICO_EMPTY': {'GSREN': 'false', 'LSREN': 'true'},
'ODDR': { 'TXCLK_POL': '0'},
'ODDRC': { 'TXCLK_POL': '0'},
'OSER4': { 'GSREN': 'false', 'LSREN': 'true', 'TXCLK_POL': '0', 'HWL': 'false'},
Expand Down Expand Up @@ -2112,33 +2113,54 @@ def iologic_mod_attrs(attrs):
attrs.pop('Q0_INIT', None)
attrs.pop('Q1_INIT', None)

def make_iodelay_attrs(in_attrs, param):
if 'IODELAY' not in param:
return
if param['IODELAY'] == 'IN':
in_attrs['INDEL'] = 'ENABLE'
else:
in_attrs['OUTDEL'] = 'ENABLE'
in_attrs['CLKOMUX'] = 'ENABLE'
in_attrs['IMARG'] = 'ENABLE'
in_attrs['INDEL_0'] = 'ENABLE'
in_attrs['INDEL_1'] = 'ENABLE'
if 'C_STATIC_DLY' not in in_attrs:
return
for i in range(1, 8):
if in_attrs['C_STATIC_DLY'][-i] == '1':
in_attrs[f'DELAY_DEL{i - 1}'] = '1'
in_attrs.pop('C_STATIC_DLY', None);

def set_iologic_attrs(db, attrs, param):
in_attrs = _iologic_default_attrs[param['IOLOGIC_TYPE']].copy()
in_attrs.update(attrs)
iologic_mod_attrs(in_attrs)
fin_attrs = set()
if 'OUTMODE' in attrs:
if attrs['OUTMODE'] != 'ODDRX1':
in_attrs['CLKODDRMUX_WRCLK'] = 'ECLK0'
if attrs['OUTMODE'] != 'ODDRX1' or param['IOLOGIC_TYPE'] == 'ODDRC':
in_attrs['LSROMUX_0'] = '1'
if param['IOLOGIC_TYPE'] == 'IOLOGICO_EMPTY':
in_attrs.pop('OUTMODE', None);
else:
in_attrs['LSROMUX_0'] = '0'
in_attrs['CLKODDRMUX_ECLK'] = 'UNKNOWN'
if param['IOLOGIC_FCLK'] in {'SPINE12', 'SPINE13'}:
in_attrs['CLKODDRMUX_ECLK'] = 'ECLK1'
elif param['IOLOGIC_FCLK'] in {'SPINE10', 'SPINE11'}:
in_attrs['CLKODDRMUX_ECLK'] = 'ECLK0'
if attrs['OUTMODE'] == 'ODDRX8' or attrs['OUTMODE'] == 'DDRENABLE16':
in_attrs['LSROMUX_0'] = '0'
if attrs['OUTMODE'] == 'DDRENABLE16':
in_attrs['OUTMODE'] = 'DDRENABLE'
in_attrs['ISI'] = 'ENABLE'
if attrs['OUTMODE'] == 'DDRENABLE':
in_attrs['ISI'] = 'ENABLE'
in_attrs['LSRIMUX_0'] = '0'
in_attrs['CLKOMUX'] = 'ENABLE'
# in_attrs['LSRMUX_LSR'] = 'INV'
if attrs['OUTMODE'] != 'ODDRX1':
in_attrs['CLKODDRMUX_WRCLK'] = 'ECLK0'
if attrs['OUTMODE'] != 'ODDRX1' or param['IOLOGIC_TYPE'] == 'ODDRC':
in_attrs['LSROMUX_0'] = '1'
else:
in_attrs['LSROMUX_0'] = '0'
in_attrs['CLKODDRMUX_ECLK'] = 'UNKNOWN'
if param['IOLOGIC_FCLK'] in {'SPINE12', 'SPINE13'}:
in_attrs['CLKODDRMUX_ECLK'] = 'ECLK1'
elif param['IOLOGIC_FCLK'] in {'SPINE10', 'SPINE11'}:
in_attrs['CLKODDRMUX_ECLK'] = 'ECLK0'
if attrs['OUTMODE'] == 'ODDRX8' or attrs['OUTMODE'] == 'DDRENABLE16':
in_attrs['LSROMUX_0'] = '0'
if attrs['OUTMODE'] == 'DDRENABLE16':
in_attrs['OUTMODE'] = 'DDRENABLE'
in_attrs['ISI'] = 'ENABLE'
if attrs['OUTMODE'] == 'DDRENABLE':
in_attrs['ISI'] = 'ENABLE'
in_attrs['LSRIMUX_0'] = '0'
in_attrs['CLKOMUX'] = 'ENABLE'
# in_attrs['LSRMUX_LSR'] = 'INV'

if 'INMODE' in attrs:
if param['IOLOGIC_TYPE'] == 'IOLOGICI_EMPTY':
Expand All @@ -2161,6 +2183,8 @@ def set_iologic_attrs(db, attrs, param):
in_attrs['ISI'] = 'ENABLE'
in_attrs['LSROMUX_0'] = '0'
in_attrs['CLKIMUX'] = 'ENABLE'
make_iodelay_attrs(in_attrs, param);
#print(in_attrs)

for k, val in in_attrs.items():
if k not in attrids.iologic_attrids:
Expand Down Expand Up @@ -2328,13 +2352,13 @@ def place(db, tilemap, bels, cst, args):

if is_himbaechel and typ in {'IOLOGIC', 'IOLOGICI', 'IOLOGICO', 'IOLOGIC_DUMMY', 'ODDR', 'ODDRC', 'OSER4',
'OSER8', 'OSER10', 'OVIDEO', 'IDDR', 'IDDRC', 'IDES4', 'IDES8', 'IDES10', 'IVIDEO',
'IOLOGICI_EMPTY'}:
'IOLOGICI_EMPTY', 'IOLOGICO_EMPTY'}:
if num[-1] in {'I', 'O'}:
num = num[:-1]
if typ == 'IOLOGIC_DUMMY':
attrs['IOLOGIC_FCLK'] = pnr['modules']['top']['cells'][attrs['MAIN_CELL']]['attributes']['IOLOGIC_FCLK']
attrs['IOLOGIC_TYPE'] = typ
if typ not in {'IDDR', 'IDDRC', 'ODDR', 'ODDRC', 'IOLOGICI_EMPTY'}:
if typ not in {'IDDR', 'IDDRC', 'ODDR', 'ODDRC', 'IOLOGICI_EMPTY', 'IOLOGICO_EMPTY'}:
# We clearly distinguish between the HCLK wires and clock
# spines at the nextpnr level by name, but in the fuse tables
# they have the same number, this is possible because the clock
Expand Down
3 changes: 3 additions & 0 deletions apycula/gowin_unpack.py
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Original file line number Diff line number Diff line change
Expand Up @@ -396,6 +396,9 @@ def parse_tile_(db, row, col, tile, default=True, noalias=False, noiostd = True)
attrvals = parse_attrvals(tile, db.logicinfo['IOLOGIC'], db.shortval[tiledata.ttyp][f'IOLOGIC{idx}'], attrids.iologic_attrids)
if not attrvals:
continue
# additional IOLOGIC components
# XXX delays and FFs in IO
# main component
if 'OUTMODE' in attrvals.keys():
# XXX skip oddr
if attrvals['OUTMODE'] in {attrids.iologic_attrvals['MODDRX1'], attrids.iologic_attrvals['ODDRX1']}:
Expand Down
18 changes: 9 additions & 9 deletions examples/himbaechel/Makefile.himbaechel
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ all: \
blinky-clkdiv-tangnano20k.fs dvi-example-tangnano20k.fs blinky-clkdiv-dhcen-tangnano20k.fs \
oddr-elvds-tangnano20k.fs pll-nanolcd-tangnano20k.fs attosoc-tangnano20k.fs \
oser4-tangnano20k.fs ovideo-tangnano20k.fs oser8-tangnano20k.fs oser10-tangnano20k.fs \
iddr-tangnano20k.fs iddrc-tangnano20k.fs \
iddr-tangnano20k.fs iddrc-tangnano20k.fs iodelay-tangnano20k.fs \
ides4-tangnano20k.fs ivideo-tangnano20k.fs ides8-tangnano20k.fs ides10-tangnano20k.fs \
bsram-pROM-tangnano20k.fs bsram-SDPB-tangnano20k.fs bsram-SP-tangnano20k.fs \
bsram-DPB-tangnano20k.fs bsram-pROMX9-tangnano20k.fs bsram-SDPX9B-tangnano20k.fs \
Expand All @@ -25,7 +25,7 @@ all: \
blinky-clkdiv-primer20k.fs dvi-example-primer20k.fs blinky-clkdiv-dhcen-primer20k.fs \
oddr-elvds-primer20k.fs pll-nanolcd-primer20k.fs attosoc-primer20k.fs \
oser4-primer20k.fs ovideo-primer20k.fs oser8-primer20k.fs oser10-primer20k.fs \
iddr-primer20k.fs iddrc-primer20k.fs \
iddr-primer20k.fs iddrc-primer20k.fs iodelay-primer20k.fs \
ides4-primer20k.fs ivideo-primer20k.fs ides8-primer20k.fs ides10-primer20k.fs \
bsram-pROM-primer20k.fs bsram-SDPB-primer20k.fs bsram-SP-primer20k.fs \
bsram-DPB-primer20k.fs bsram-pROMX9-primer20k.fs bsram-SDPX9B-primer20k.fs \
Expand All @@ -39,7 +39,7 @@ all: \
blinky-tangnano.fs shift-tangnano.fs blinky-tbuf-tangnano.fs blinky-oddr-tangnano.fs \
blinky-osc-tangnano.fs elvds-tangnano.fs oddr-elvds-tangnano.fs pll-nanolcd-tangnano.fs \
oser4-tangnano.fs ovideo-tangnano.fs oser8-tangnano.fs oser10-tangnano.fs \
iddr-tangnano.fs iddrc-tangnano.fs \
iddr-tangnano.fs iddrc-tangnano.fs iodelay-tangnano.fs \
ides4-tangnano.fs ivideo-tangnano.fs ides8-tangnano.fs ides10-tangnano.fs \
bsram-pROM-tangnano.fs bsram-SDPB-tangnano.fs bsram-DPB-tangnano.fs \
bsram-SP-tangnano.fs bsram-pROMX9-tangnano.fs bsram-SDPX9B-tangnano.fs \
Expand All @@ -48,7 +48,7 @@ all: \
blinky-tangnano1k.fs shift-tangnano1k.fs blinky-tbuf-tangnano1k.fs blinky-oddr-tangnano1k.fs \
blinky-osc-tangnano1k.fs elvds-tangnano1k.fs oddr-elvds-tangnano1k.fs pll-nanolcd-tangnano1k.fs \
oser4-tangnano1k.fs ovideo-tangnano1k.fs oser8-tangnano1k.fs oser10-tangnano1k.fs \
iddr-tangnano1k.fs iddrc-tangnano1k.fs \
iddr-tangnano1k.fs iddrc-tangnano1k.fs iodelay-tangnano1k.fs \
ides4-tangnano1k.fs ivideo-tangnano1k.fs ides8-tangnano1k.fs ides10-tangnano1k.fs \
bsram-pROM-tangnano1k.fs bsram-SDPB-tangnano1k.fs bsram-DPB16-tangnano1k.fs \
bsram-SP-tangnano1k.fs bsram-pROMX9-tangnano1k.fs bsram-SDPX9B-tangnano1k.fs \
Expand All @@ -61,7 +61,7 @@ all: \
oser4-tangnano4k.fs ovideo-tangnano4k.fs oser8-tangnano4k.fs oser10-tangnano4k.fs \
iddr-tangnano4k.fs iddrc-tangnano4k.fs ides16-tangnano4k.fs \
ides4-tangnano4k.fs ivideo-tangnano4k.fs ides8-tangnano4k.fs ides10-tangnano4k.fs \
oser10-tlvds-tangnano4k.fs \
oser10-tlvds-tangnano4k.fs iodelay-tangnano4k.fs \
femto-riscv-15-tangnano4k.fs femto-riscv-16-tangnano4k.fs femto-riscv-18-tangnano4k.fs \
dsp-mult18x18-tangnano4k.fs dsp-mult36x36-tangnano4k.fs dsp-padd9-tangnano4k.fs dsp-padd18-tangnano4k.fs \
dsp-mult9x9-tangnano4k.fs dsp-alu54d-tangnano4k.fs dsp-multalu18x18-tangnano4k.fs \
Expand All @@ -74,7 +74,7 @@ all: \
blinky-osc-tangnano9k.fs tlvds-tangnano9k.fs elvds-tangnano9k.fs oddr-tlvds-tangnano9k.fs \
oddr-elvds-tangnano9k.fs pll-nanolcd-tangnano9k.fs oser16-tangnano9k.fs attosoc-tangnano9k.fs \
oser4-tangnano9k.fs ovideo-tangnano9k.fs oser8-tangnano9k.fs oser10-tangnano9k.fs \
iddr-tangnano9k.fs iddrc-tangnano9k.fs \
iddr-tangnano9k.fs iddrc-tangnano9k.fs iodelay-tangnano9k.fs \
ides4-tangnano9k.fs ivideo-tangnano9k.fs ides8-tangnano9k.fs ides10-tangnano9k.fs \
bsram-pROM-tangnano9k.fs bsram-SDPB-tangnano9k.fs bsram-SP-tangnano9k.fs \
bsram-DPB-tangnano9k.fs bsram-pROMX9-tangnano9k.fs bsram-SDPX9B-tangnano9k.fs \
Expand All @@ -90,7 +90,7 @@ all: \
blinky-osc-szfpga.fs tlvds-szfpga.fs elvds-szfpga.fs oddr-tlvds-szfpga.fs \
oddr-elvds-szfpga.fs blinky-pll-szfpga.fs oser16-szfpga.fs attosoc-szfpga.fs \
oser4-szfpga.fs ovideo-szfpga.fs oser8-szfpga.fs oser10-szfpga.fs \
iddr-szfpga.fs iddrc-szfpga.fs ides16-szfpga.fs \
iddr-szfpga.fs iddrc-szfpga.fs ides16-szfpga.fs iodelay-szfpga.fs \
ides4-szfpga.fs ivideo-szfpga.fs ides8-szfpga.fs ides10-szfpga.fs \
bsram-pROM-szfpga.fs bsram-SDPB-szfpga.fs bsram-SP-szfpga.fs \
bsram-pROMX9-szfpga.fs bsram-SDPX9B-szfpga.fs \
Expand All @@ -104,7 +104,7 @@ all: \
blinky-osc-tec0117.fs tlvds-tec0117.fs elvds-tec0117.fs oddr-tlvds-tec0117.fs \
oddr-elvds-tec0117.fs blinky-pll-tec0117.fs oser16-tec0117.fs attosoc-tec0117.fs \
oser4-tec0117.fs ovideo-tec0117.fs oser8-tec0117.fs oser10-tec0117.fs \
iddr-tec0117.fs iddrc-tec0117.fs ides16-tec0117.fs \
iddr-tec0117.fs iddrc-tec0117.fs ides16-tec0117.fs iodelay-tec0117.fs \
ides4-tec0117.fs ivideo-tec0117.fs ides8-tec0117.fs ides10-tec0117.fs \
dsp-mult18x18-tec0117.fs dsp-mult36x36-tec0117.fs dsp-padd9-tec0117.fs dsp-padd18-tec0117.fs \
dsp-mult9x9-tec0117.fs dsp-alu54d-tec0117.fs dsp-multalu18x18-tec0117.fs \
Expand All @@ -114,7 +114,7 @@ all: \
blinky-osc-runber.fs tlvds-runber.fs elvds-runber.fs oddr-tlvds-runber.fs \
oddr-elvds-runber.fs blinky-pll-runber.fs \
oser4-runber.fs ovideo-runber.fs oser8-runber.fs oser10-runber.fs \
iddr-runber.fs iddrc-runber.fs \
iddr-runber.fs iddrc-runber.fs iodelay-runber.fs \
ides4-runber.fs ivideo-runber.fs ides8-runber.fs ides10-runber.fs \
dsp-mult36x36-runber.fs dsp-padd9-runber.fs dsp-padd18-runber.fs \
dsp-mult9x9-runber.fs dsp-alu54d-runber.fs dsp-multalu18x18-runber.fs \
Expand Down
14 changes: 13 additions & 1 deletion examples/himbaechel/blinky-oddr.v
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Original file line number Diff line number Diff line change
Expand Up @@ -26,11 +26,23 @@ assign ctr_d = ctr_q + 1'b1;
assign led[`LEDS_NR-1:2] = {(`LEDS_NR - 2){1'b1}};
assign led[0] = ctr_q[24:24];

wire aux_wire;

IODELAY delay0(
.DI(aux_wire),
.DO(led[1]),
.SDTAP(1'b0),
.SETN(1'b1),
.VALUE(1'b0),
.DF()
);
defparam delay0.C_STATIC_DLY=100;

ODDRC oddr_0(
.D0(1'b0),
.D1(1'b1),
.CLK(ctr_q[24:24]),
.Q0(led[1]),
.Q0(aux_wire),
.Q1(),
.TX(1'b1),
.CLEAR(!key)
Expand Down
35 changes: 35 additions & 0 deletions examples/himbaechel/iodelay.v
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Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
/* */
module top (
input clk,
input key_i,
input rst_i,
input data_i,
input fclk_i,
input LCD_CLK,
input LCD_SYNC,
output [5:0] led
);


IODELAY id0(
.DO(led[0]),
.DI(rst_i),
.DF(led[1]),
.SDTAP(data_i),
.SETN(fclk_i),
.VALUE(key_i)
);
defparam id0.C_STATIC_DLY='d96;

IODELAY od1(
.DO(led[2]),
.DI(LCD_CLK),
.DF(led[3]),
.SDTAP(data_i),
.SETN(fclk_i),
.VALUE(key_i)
);
defparam od1.C_STATIC_DLY='d63;

endmodule

14 changes: 13 additions & 1 deletion examples/himbaechel/oser4.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,18 @@ module top(input wire clk,
output wire pclk_o,
output wire fclk_o);

wire aux_wire;
IODELAY delay0(
.DI(aux_wire),
.DO(oser_out),
.SDTAP(1'b0),
.SETN(1'b1),
.VALUE(1'b0),
.DF()
);

defparam delay0.C_STATIC_DLY=100;

wire rst = rst_i ^ `INV_BTN;
OSER4 os(
.D0(1'b0),
Expand All @@ -21,7 +33,7 @@ module top(input wire clk,
.FCLK(fclk_w),
.PCLK(pclk_w),
.RESET(1'b0),
.Q0(oser_out),
.Q0(aux_wire),
.Q1()
);
defparam os.GSREN = "false";
Expand Down
5 changes: 4 additions & 1 deletion examples/himbaechel/runber.cst
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Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,9 @@ IO_LOC "LED_R" 25;
IO_LOC "LED_G" 26;
IO_LOC "LED_B" 23;

IO_LOC "LCD_SYNC" 29;
IO_LOC "LCD_CLK" 44;

// oser
IO_LOC "oser_out" 25;
IO_LOC "io16" 25;
Expand All @@ -34,7 +37,7 @@ IO_LOC "fclk_o" 29;

// ides
IO_LOC "fclk_i" 54;
IO_LOC "data_i" 25;
IO_LOC "data_i" 30;
IO_LOC "q_o[0]" 38;
IO_LOC "q_o[1]" 39;
IO_LOC "q_o[2]" 40;
Expand Down
4 changes: 4 additions & 0 deletions examples/himbaechel/tangnano.cst
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,10 @@ IO_LOC "LED_R" 16;
IO_LOC "LED_G" 17;
IO_LOC "LED_B" 18;

IO_LOC "led[3]" 42;
IO_LOC "led[4]" 43;
IO_LOC "led[5]" 44;

// ides
IO_LOC "fclk_i" 45;
IO_LOC "data_i" 41;
Expand Down
7 changes: 7 additions & 0 deletions examples/himbaechel/tangnano1k.cst
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,13 @@ IO_PORT "clk" IO_TYPE=LVCMOS33;
IO_LOC "elvds_p" 40;
IO_LOC "elvds_n" 39;

IO_LOC "led[3]" 24;
IO_PORT "led[3]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8;
IO_LOC "led[4]" 23;
IO_PORT "led[4]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8;
IO_LOC "led[5]" 22;
IO_PORT "led[5]" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8;

IO_LOC "LED_R" 9;
IO_PORT "LED_R" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8;
IO_LOC "LED_G" 10;
Expand Down
3 changes: 3 additions & 0 deletions examples/himbaechel/tangnano4k.cst
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,9 @@ IO_LOC "LED_R" 34;
IO_LOC "LED_G" 35;
IO_LOC "LED_B" 29;

IO_LOC "LCD_CLK" 47;
IO_LOC "LCD_SYNC" 48;

// ides
IO_LOC "data_i" 43;
IO_LOC "fclk_i" 46;
Expand Down
2 changes: 1 addition & 1 deletion examples/himbaechel/tec0117.cst
View file
Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,7 @@ IO_PORT "fclk_o" IO_TYPE=LVCMOS33;
// ides
IO_LOC "fclk_i" 18;
IO_PORT "fclk_i" IO_TYPE=LVCMOS33;
IO_LOC "data_i" 86;
IO_LOC "data_i" 71;
IO_PORT "data_i" IO_TYPE=LVCMOS33;
IO_LOC "q_o[0]" 20;
IO_PORT "q_o[0]" IO_TYPE=LVCMOS33;
Expand Down

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