| Unit under | Testing Directory | File required | Runtime |
|---|---|---|---|
| Fetch_stage | unit test fetch stage | fetch_stage.vhd + fetchStage_tb.vhd | 15ns |
| Decode_stage*** | unit test decode stage | decode_stage.vhd + decodeStage_tb.vhd + register_file.vhd | 20ns |
| Register_file | component test register file | register_file.vhd + register_file_tb.vhd | 20ns |
| Execute_stage | unit test execute stage | execute_stage.vhd + executeStage_tb.vhd + TWOMUX.vhd + ADD.vhd + FIVEMUX.vhd + ALU.vhd | 16ns |
| ALU | component test ALU | ALU.vhd + ALUUnit.vhd | 10ns |
| Memory_stage | unit test memory stage | memory_stage.vhd + memoryStage_tb.vhd | 20ns |
| Writeback_stage | unit test write back stage | writeback_stage.vhd + writebackStage_tb.vhd + TWOMUX.vhd | 6ns |
| Memory | component test memory | memory.vhd + memory_tb.vhd | 15ns |
*** Decode stage unit testing may have compilatoin errors for one file. In that case, compile only the failed file again and it will compile successfully. It is an compile order issue.
- Go to the benchmark1 directory
- Use Modelsim to open the project file: benchmark1.mpf
- Make sure all files needed to run are included:
- Run the command:
source benchmark1_tb.tclin the console - The console may report error:
- Ignore the error and goto wave window
- Make sure the time to run is 6.5ns for testbench1
- Show the result:
Note: In this project, we assume that the end of program is not an infinite loop instruction. Our CPU will determine when is the end of the instruction by itself since when loading the instructions from "program.txt", we assigned the rest of instruction memory as undefined.
- Go to the benchmark2 directory
- Use Modelsim to open the project file: processor.mpf
- Make sure all files needed to run are included:
- Run the command:
source final_tb.tclin the console - The console may report error:
- Ignore the error and goto wave window
- Make sure the time to run is 55ns for testbench2
- Show the result:
